forked from luck/tmp_suning_uos_patched
c2a3e84f95
Reading from the DCC grabs a character from the buffer and clears the status bit. Since this is a context-changing operation, instructions following the character read that rely on the status bit being accurate need to be synchronized with an ISB. In this case, the status bit check needs to execute after the character read otherwise we run the risk of reading the character and checking the status bit before the read can clear the status bit in the first place. When this happens, the user will see the same character they typed twice, instead of once. Add an ISB after the read and the write, so that the status check is synchronized with the read/write operations. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: stable <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
107 lines
2.3 KiB
C
107 lines
2.3 KiB
C
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <asm/processor.h>
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#include "hvc_console.h"
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/* DCC Status Bits */
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#define DCC_STATUS_RX (1 << 30)
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#define DCC_STATUS_TX (1 << 29)
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static inline u32 __dcc_getstatus(void)
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{
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u32 __ret;
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asm volatile("mrc p14, 0, %0, c0, c1, 0 @ read comms ctrl reg"
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: "=r" (__ret) : : "cc");
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return __ret;
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}
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static inline char __dcc_getchar(void)
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{
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char __c;
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asm volatile("mrc p14, 0, %0, c0, c5, 0 @ read comms data reg"
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: "=r" (__c));
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isb();
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return __c;
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}
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static inline void __dcc_putchar(char c)
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{
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asm volatile("mcr p14, 0, %0, c0, c5, 0 @ write a char"
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: /* no output register */
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: "r" (c));
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isb();
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}
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static int hvc_dcc_put_chars(uint32_t vt, const char *buf, int count)
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{
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int i;
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for (i = 0; i < count; i++) {
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while (__dcc_getstatus() & DCC_STATUS_TX)
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cpu_relax();
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__dcc_putchar(buf[i]);
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}
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return count;
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}
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static int hvc_dcc_get_chars(uint32_t vt, char *buf, int count)
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{
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int i;
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for (i = 0; i < count; ++i)
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if (__dcc_getstatus() & DCC_STATUS_RX)
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buf[i] = __dcc_getchar();
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else
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break;
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return i;
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}
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static const struct hv_ops hvc_dcc_get_put_ops = {
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.get_chars = hvc_dcc_get_chars,
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.put_chars = hvc_dcc_put_chars,
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};
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static int __init hvc_dcc_console_init(void)
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{
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hvc_instantiate(0, 0, &hvc_dcc_get_put_ops);
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return 0;
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}
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console_initcall(hvc_dcc_console_init);
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static int __init hvc_dcc_init(void)
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{
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hvc_alloc(0, 0, &hvc_dcc_get_put_ops, 128);
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return 0;
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}
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device_initcall(hvc_dcc_init);
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