forked from luck/tmp_suning_uos_patched
482 lines
13 KiB
C
482 lines
13 KiB
C
/*
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* sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
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*
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* Maintained by: Jeremy Higdon @ SGI
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2004 SGI
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*
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* Bits from Jeff Garzik, Copyright RedHat, Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Vitesse hardware documentation presumably available under NDA.
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* Intel 31244 (same hardware interface) documentation presumably
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* available from http://developer.intel.com/
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "sata_vsc"
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#define DRV_VERSION "1.2"
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enum {
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/* Interrupt register offsets (from chip base address) */
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VSC_SATA_INT_STAT_OFFSET = 0x00,
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VSC_SATA_INT_MASK_OFFSET = 0x04,
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/* Taskfile registers offsets */
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VSC_SATA_TF_CMD_OFFSET = 0x00,
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VSC_SATA_TF_DATA_OFFSET = 0x00,
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VSC_SATA_TF_ERROR_OFFSET = 0x04,
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VSC_SATA_TF_FEATURE_OFFSET = 0x06,
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VSC_SATA_TF_NSECT_OFFSET = 0x08,
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VSC_SATA_TF_LBAL_OFFSET = 0x0c,
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VSC_SATA_TF_LBAM_OFFSET = 0x10,
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VSC_SATA_TF_LBAH_OFFSET = 0x14,
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VSC_SATA_TF_DEVICE_OFFSET = 0x18,
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VSC_SATA_TF_STATUS_OFFSET = 0x1c,
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VSC_SATA_TF_COMMAND_OFFSET = 0x1d,
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VSC_SATA_TF_ALTSTATUS_OFFSET = 0x28,
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VSC_SATA_TF_CTL_OFFSET = 0x29,
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/* DMA base */
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VSC_SATA_UP_DESCRIPTOR_OFFSET = 0x64,
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VSC_SATA_UP_DATA_BUFFER_OFFSET = 0x6C,
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VSC_SATA_DMA_CMD_OFFSET = 0x70,
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/* SCRs base */
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VSC_SATA_SCR_STATUS_OFFSET = 0x100,
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VSC_SATA_SCR_ERROR_OFFSET = 0x104,
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VSC_SATA_SCR_CONTROL_OFFSET = 0x108,
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/* Port stride */
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VSC_SATA_PORT_OFFSET = 0x200,
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/* Error interrupt status bit offsets */
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VSC_SATA_INT_ERROR_CRC = 0x40,
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VSC_SATA_INT_ERROR_T = 0x20,
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VSC_SATA_INT_ERROR_P = 0x10,
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VSC_SATA_INT_ERROR_R = 0x8,
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VSC_SATA_INT_ERROR_E = 0x4,
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VSC_SATA_INT_ERROR_M = 0x2,
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VSC_SATA_INT_PHY_CHANGE = 0x1,
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VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC | VSC_SATA_INT_ERROR_T | \
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VSC_SATA_INT_ERROR_P | VSC_SATA_INT_ERROR_R | \
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VSC_SATA_INT_ERROR_E | VSC_SATA_INT_ERROR_M | \
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VSC_SATA_INT_PHY_CHANGE),
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};
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#define is_vsc_sata_int_err(port_idx, int_status) \
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(int_status & (VSC_SATA_INT_ERROR << (8 * port_idx)))
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static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
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{
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if (sc_reg > SCR_CONTROL)
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return 0xffffffffU;
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return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
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}
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static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
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u32 val)
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{
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if (sc_reg > SCR_CONTROL)
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return;
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writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
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}
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static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
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{
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void __iomem *mask_addr;
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u8 mask;
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mask_addr = ap->host_set->mmio_base +
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VSC_SATA_INT_MASK_OFFSET + ap->port_no;
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mask = readb(mask_addr);
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if (ctl & ATA_NIEN)
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mask |= 0x80;
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else
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mask &= 0x7F;
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writeb(mask, mask_addr);
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}
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static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
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/*
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* The only thing the ctl register is used for is SRST.
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* That is not enabled or disabled via tf_load.
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* However, if ATA_NIEN is changed, then we need to change the interrupt register.
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*/
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if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
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ap->last_ctl = tf->ctl;
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vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
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}
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if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
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writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
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writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
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writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
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writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
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writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
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} else if (is_addr) {
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writew(tf->feature, ioaddr->feature_addr);
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writew(tf->nsect, ioaddr->nsect_addr);
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writew(tf->lbal, ioaddr->lbal_addr);
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writew(tf->lbam, ioaddr->lbam_addr);
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writew(tf->lbah, ioaddr->lbah_addr);
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}
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if (tf->flags & ATA_TFLAG_DEVICE)
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writeb(tf->device, ioaddr->device_addr);
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ata_wait_idle(ap);
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}
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static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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u16 nsect, lbal, lbam, lbah, feature;
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tf->command = ata_check_status(ap);
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tf->device = readw(ioaddr->device_addr);
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feature = readw(ioaddr->error_addr);
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nsect = readw(ioaddr->nsect_addr);
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lbal = readw(ioaddr->lbal_addr);
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lbam = readw(ioaddr->lbam_addr);
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lbah = readw(ioaddr->lbah_addr);
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tf->feature = feature;
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tf->nsect = nsect;
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tf->lbal = lbal;
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tf->lbam = lbam;
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tf->lbah = lbah;
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if (tf->flags & ATA_TFLAG_LBA48) {
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tf->hob_feature = feature >> 8;
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tf->hob_nsect = nsect >> 8;
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tf->hob_lbal = lbal >> 8;
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tf->hob_lbam = lbam >> 8;
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tf->hob_lbah = lbah >> 8;
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}
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}
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/*
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* vsc_sata_interrupt
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*
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* Read the interrupt register and process for the devices that have them pending.
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*/
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static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance,
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struct pt_regs *regs)
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{
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struct ata_host_set *host_set = dev_instance;
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unsigned int i;
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unsigned int handled = 0;
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u32 int_status;
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spin_lock(&host_set->lock);
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int_status = readl(host_set->mmio_base + VSC_SATA_INT_STAT_OFFSET);
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for (i = 0; i < host_set->n_ports; i++) {
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if (int_status & ((u32) 0xFF << (8 * i))) {
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struct ata_port *ap;
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ap = host_set->ports[i];
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if (is_vsc_sata_int_err(i, int_status)) {
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u32 err_status;
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printk(KERN_DEBUG "%s: ignoring interrupt(s)\n", __FUNCTION__);
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err_status = ap ? vsc_sata_scr_read(ap, SCR_ERROR) : 0;
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vsc_sata_scr_write(ap, SCR_ERROR, err_status);
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handled++;
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}
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if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
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struct ata_queued_cmd *qc;
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qc = ata_qc_from_tag(ap, ap->active_tag);
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if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
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handled += ata_host_intr(ap, qc);
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else if (is_vsc_sata_int_err(i, int_status)) {
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/*
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* On some chips (i.e. Intel 31244), an error
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* interrupt will sneak in at initialization
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* time (phy state changes). Clearing the SCR
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* error register is not required, but it prevents
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* the phy state change interrupts from recurring
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* later.
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*/
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u32 err_status;
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err_status = vsc_sata_scr_read(ap, SCR_ERROR);
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printk(KERN_DEBUG "%s: clearing interrupt, "
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"status %x; sata err status %x\n",
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__FUNCTION__,
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int_status, err_status);
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vsc_sata_scr_write(ap, SCR_ERROR, err_status);
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/* Clear interrupt status */
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ata_chk_status(ap);
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handled++;
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}
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}
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}
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}
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spin_unlock(&host_set->lock);
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return IRQ_RETVAL(handled);
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}
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static struct scsi_host_template vsc_sata_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.bios_param = ata_std_bios_param,
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};
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static const struct ata_port_operations vsc_sata_ops = {
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.port_disable = ata_port_disable,
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.tf_load = vsc_sata_tf_load,
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.tf_read = vsc_sata_tf_read,
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.exec_command = ata_exec_command,
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.check_status = ata_check_status,
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.dev_select = ata_std_dev_select,
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.phy_reset = sata_phy_reset,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.eng_timeout = ata_eng_timeout,
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.irq_handler = vsc_sata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.scr_read = vsc_sata_scr_read,
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.scr_write = vsc_sata_scr_write,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = ata_pci_host_stop,
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};
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static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
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{
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port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
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port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
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port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
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port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
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port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
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port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
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port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
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port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
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port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
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port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
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port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
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port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
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port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
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port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
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port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
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writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
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writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
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}
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static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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static int printed_version;
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struct ata_probe_ent *probe_ent = NULL;
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unsigned long base;
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int pci_dev_busy = 0;
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void __iomem *mmio_base;
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int rc;
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
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rc = pci_enable_device(pdev);
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if (rc)
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return rc;
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/*
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* Check if we have needed resource mapped.
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*/
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if (pci_resource_len(pdev, 0) == 0) {
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rc = -ENODEV;
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goto err_out;
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}
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rc = pci_request_regions(pdev, DRV_NAME);
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if (rc) {
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pci_dev_busy = 1;
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goto err_out;
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}
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/*
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* Use 32 bit DMA mask, because 64 bit address support is poor.
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*/
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rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
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if (rc)
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goto err_out_regions;
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rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
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if (rc)
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goto err_out_regions;
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probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
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if (probe_ent == NULL) {
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rc = -ENOMEM;
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goto err_out_regions;
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}
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memset(probe_ent, 0, sizeof(*probe_ent));
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probe_ent->dev = pci_dev_to_dev(pdev);
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INIT_LIST_HEAD(&probe_ent->node);
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mmio_base = pci_iomap(pdev, 0, 0);
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if (mmio_base == NULL) {
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rc = -ENOMEM;
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goto err_out_free_ent;
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}
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base = (unsigned long) mmio_base;
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/*
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* Due to a bug in the chip, the default cache line size can't be used
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*/
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pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
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probe_ent->sht = &vsc_sata_sht;
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probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_MMIO | ATA_FLAG_SATA_RESET;
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probe_ent->port_ops = &vsc_sata_ops;
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probe_ent->n_ports = 4;
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probe_ent->irq = pdev->irq;
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probe_ent->irq_flags = SA_SHIRQ;
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probe_ent->mmio_base = mmio_base;
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/* We don't care much about the PIO/UDMA masks, but the core won't like us
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* if we don't fill these
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*/
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probe_ent->pio_mask = 0x1f;
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probe_ent->mwdma_mask = 0x07;
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probe_ent->udma_mask = 0x7f;
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/* We have 4 ports per PCI function */
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vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
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vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
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vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
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vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);
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pci_set_master(pdev);
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/*
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* Config offset 0x98 is "Extended Control and Status Register 0"
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* Default value is (1 << 28). All bits except bit 28 are reserved in
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* DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
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* If bit 28 is clear, each port has its own LED.
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*/
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pci_write_config_dword(pdev, 0x98, 0);
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/* FIXME: check ata_device_add return value */
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ata_device_add(probe_ent);
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kfree(probe_ent);
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return 0;
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err_out_free_ent:
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kfree(probe_ent);
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err_out_regions:
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pci_release_regions(pdev);
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err_out:
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if (!pci_dev_busy)
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pci_disable_device(pdev);
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return rc;
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}
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/*
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* 0x1725/0x7174 is the Vitesse VSC-7174
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* 0x8086/0x3200 is the Intel 31244, which is supposed to be identical
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* compatibility is untested as of yet
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*/
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static const struct pci_device_id vsc_sata_pci_tbl[] = {
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{ 0x1725, 0x7174, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
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{ 0x8086, 0x3200, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
|
|
{ }
|
|
};
|
|
|
|
|
|
static struct pci_driver vsc_sata_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = vsc_sata_pci_tbl,
|
|
.probe = vsc_sata_init_one,
|
|
.remove = ata_pci_remove_one,
|
|
};
|
|
|
|
|
|
static int __init vsc_sata_init(void)
|
|
{
|
|
return pci_module_init(&vsc_sata_pci_driver);
|
|
}
|
|
|
|
|
|
static void __exit vsc_sata_exit(void)
|
|
{
|
|
pci_unregister_driver(&vsc_sata_pci_driver);
|
|
}
|
|
|
|
|
|
MODULE_AUTHOR("Jeremy Higdon");
|
|
MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
module_init(vsc_sata_init);
|
|
module_exit(vsc_sata_exit);
|