Will Deacon db6f41063c arm64: mm: don't treat user cache maintenance faults as writes ... On arm64, cache maintenance faults appear as data aborts with the CM bit set in the ESR. The WnR bit, usually used to distinguish between faulting loads and stores, always reads as 1 and (slightly confusingly) the instructions are treated as reads by the architecture. This patch fixes our fault handling code to treat cache maintenance faults in the same way as loads. Signed-off-by: Will Deacon <will.deacon@arm.com> Cc: <stable@vger.kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>		2013-07-19 15:49:44 +01:00
..
cache.S
context.c
copypage.c
dma-mapping.c
extable.c
fault.c	arm64: mm: don't treat user cache maintenance faults as writes	2013-07-19 15:49:44 +01:00
flush.c
hugetlbpage.c
init.c	mm/microblaze: prepare for removing num_physpages and simplify mem_init()	2013-07-03 16:07:36 -07:00
ioremap.c
Makefile
mm.h
mmap.c	mm: remove free_area_cache	2013-07-10 18:11:34 -07:00
mmu.c
pgd.c
proc-macros.S
proc.S
tlb.S