forked from luck/tmp_suning_uos_patched
5a1aca4469
Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit4249548454("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit443c44032a("MIPS: Always clear FCSR cause bits after emulation"), * commit64bedffe49("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commitb1442d39fa("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
98 lines
3.0 KiB
C
98 lines
3.0 KiB
C
/*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Further private data for which no space exists in mips_fpu_struct.
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* This should be subsumed into the mips_fpu_struct structure as
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* defined in processor.h as soon as the absurd wired absolute assembler
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* offsets become dynamic at compile time.
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*
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* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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*/
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#ifndef _ASM_FPU_EMULATOR_H
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#define _ASM_FPU_EMULATOR_H
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#include <linux/sched.h>
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#include <asm/dsemul.h>
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#include <asm/thread_info.h>
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#include <asm/inst.h>
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#include <asm/local.h>
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#include <asm/processor.h>
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#ifdef CONFIG_DEBUG_FS
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struct mips_fpu_emulator_stats {
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unsigned long emulated;
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unsigned long loads;
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unsigned long stores;
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unsigned long cp1ops;
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unsigned long cp1xops;
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unsigned long errors;
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unsigned long ieee754_inexact;
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unsigned long ieee754_underflow;
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unsigned long ieee754_overflow;
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unsigned long ieee754_zerodiv;
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unsigned long ieee754_invalidop;
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unsigned long ds_emul;
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};
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DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
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#define MIPS_FPU_EMU_INC_STATS(M) \
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do { \
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preempt_disable(); \
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__this_cpu_inc(fpuemustats.M); \
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preempt_enable(); \
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} while (0)
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#else
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#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
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#endif /* CONFIG_DEBUG_FS */
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extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
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struct mips_fpu_struct *ctx, int has_fpu,
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void *__user *fault_addr);
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void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
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struct task_struct *tsk);
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int process_fpemu_return(int sig, void __user *fault_addr,
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unsigned long fcr31);
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int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
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unsigned long *contpc);
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int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
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unsigned long *contpc);
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#define SIGNALLING_NAN 0x7ff800007ff80000LL
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static inline void fpu_emulator_init_fpu(void)
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{
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struct task_struct *t = current;
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int i;
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for (i = 0; i < 32; i++)
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set_fpr64(&t->thread.fpu.fpr[i], 0, SIGNALLING_NAN);
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}
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/*
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* Mask the FCSR Cause bits according to the Enable bits, observing
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* that Unimplemented is always enabled.
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*/
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static inline unsigned long mask_fcr31_x(unsigned long fcr31)
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{
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return fcr31 & (FPU_CSR_UNI_X |
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((fcr31 & FPU_CSR_ALL_E) <<
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(ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E))));
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}
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#endif /* _ASM_FPU_EMULATOR_H */
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