forked from luck/tmp_suning_uos_patched
ae7a3f13ab
Power Gates must to be always enabled. Signed-off-by: Alberto Panizzo <maramaopercheseimorto@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
345 lines
8.5 KiB
C
345 lines
8.5 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <linux/smsc911x.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/mc13783.h>
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#include <linux/spi/spi.h>
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#include <linux/regulator/machine.h>
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#include <mach/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/memory.h>
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#include <asm/mach/map.h>
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#include <mach/common.h>
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#include <mach/board-mx31_3ds.h>
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#include <mach/imx-uart.h>
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#include <mach/iomux-mx3.h>
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#include <mach/mxc_nand.h>
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#include <mach/spi.h>
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#include "devices.h"
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/*!
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* @file mx31_3ds.c
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*
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* @brief This file contains the board-specific initialization routines.
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*
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* @ingroup System
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*/
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static int mx31_3ds_pins[] = {
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/* UART1 */
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MX31_PIN_CTS1__CTS1,
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MX31_PIN_RTS1__RTS1,
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MX31_PIN_TXD1__TXD1,
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MX31_PIN_RXD1__RXD1,
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IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
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/* SPI 1 */
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MX31_PIN_CSPI2_SCLK__SCLK,
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MX31_PIN_CSPI2_MOSI__MOSI,
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MX31_PIN_CSPI2_MISO__MISO,
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MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
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MX31_PIN_CSPI2_SS0__SS0,
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MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
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/* MC13783 IRQ */
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IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
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};
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/* Regulators */
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static struct regulator_init_data pwgtx_init = {
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.constraints = {
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.boot_on = 1,
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.always_on = 1,
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},
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};
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static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
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{
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.id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
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.init_data = &pwgtx_init,
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}, {
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.id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
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.init_data = &pwgtx_init,
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},
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};
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/* MC13783 */
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static struct mc13783_platform_data mc13783_pdata __initdata = {
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.regulators = mx31_3ds_regulators,
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.num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
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.flags = MC13783_USE_REGULATOR,
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};
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/* SPI */
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static int spi1_internal_chipselect[] = {
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MXC_SPI_CS(0),
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MXC_SPI_CS(2),
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};
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static struct spi_imx_master spi1_pdata = {
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.chipselect = spi1_internal_chipselect,
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.num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
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};
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static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
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{
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.modalias = "mc13783",
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.max_speed_hz = 1000000,
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.bus_num = 1,
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.chip_select = 1, /* SS2 */
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.platform_data = &mc13783_pdata,
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.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
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.mode = SPI_CS_HIGH,
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},
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};
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/*
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* NAND Flash
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*/
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static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
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.width = 1,
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.hw_ecc = 1,
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#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
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.flash_bbt = 1,
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#endif
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};
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static struct imxuart_platform_data uart_pdata = {
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.flags = IMXUART_HAVE_RTSCTS,
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};
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/*
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* Support for the SMSC9217 on the Debug board.
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*/
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static struct smsc911x_platform_config smsc911x_config = {
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.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
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.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
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.flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
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.phy_interface = PHY_INTERFACE_MODE_MII,
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};
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static struct resource smsc911x_resources[] = {
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{
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.start = LAN9217_BASE_ADDR,
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.end = LAN9217_BASE_ADDR + 0xff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = EXPIO_INT_ENET,
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.end = EXPIO_INT_ENET,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device smsc911x_device = {
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.name = "smsc911x",
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.id = -1,
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.num_resources = ARRAY_SIZE(smsc911x_resources),
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.resource = smsc911x_resources,
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.dev = {
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.platform_data = &smsc911x_config,
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},
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};
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/*
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* Routines for the CPLD on the debug board. It contains a CPLD handling
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* LEDs, switches, interrupts for Ethernet.
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*/
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static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
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{
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uint32_t imr_val;
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uint32_t int_valid;
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uint32_t expio_irq;
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imr_val = __raw_readw(CPLD_INT_MASK_REG);
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int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
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expio_irq = MXC_EXP_IO_BASE;
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for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
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if ((int_valid & 1) == 0)
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continue;
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generic_handle_irq(expio_irq);
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}
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}
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/*
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* Disable an expio pin's interrupt by setting the bit in the imr.
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* @param irq an expio virtual irq number
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*/
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static void expio_mask_irq(uint32_t irq)
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{
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uint16_t reg;
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uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
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/* mask the interrupt */
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reg = __raw_readw(CPLD_INT_MASK_REG);
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reg |= 1 << expio;
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__raw_writew(reg, CPLD_INT_MASK_REG);
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}
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/*
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* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
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* @param irq an expanded io virtual irq number
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*/
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static void expio_ack_irq(uint32_t irq)
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{
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uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
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/* clear the interrupt status */
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__raw_writew(1 << expio, CPLD_INT_RESET_REG);
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__raw_writew(0, CPLD_INT_RESET_REG);
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/* mask the interrupt */
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expio_mask_irq(irq);
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}
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/*
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* Enable a expio pin's interrupt by clearing the bit in the imr.
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* @param irq a expio virtual irq number
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*/
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static void expio_unmask_irq(uint32_t irq)
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{
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uint16_t reg;
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uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
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/* unmask the interrupt */
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reg = __raw_readw(CPLD_INT_MASK_REG);
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reg &= ~(1 << expio);
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__raw_writew(reg, CPLD_INT_MASK_REG);
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}
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static struct irq_chip expio_irq_chip = {
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.ack = expio_ack_irq,
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.mask = expio_mask_irq,
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.unmask = expio_unmask_irq,
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};
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static int __init mx31_3ds_init_expio(void)
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{
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int i;
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int ret;
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/* Check if there's a debug board connected */
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if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
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(__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
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(__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
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/* No Debug board found */
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return -ENODEV;
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}
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pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
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__raw_readw(CPLD_CODE_VER_REG));
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/*
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* Configure INT line as GPIO input
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*/
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ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
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if (ret)
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pr_warning("could not get LAN irq gpio\n");
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else
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gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
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/* Disable the interrupts and clear the status */
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__raw_writew(0, CPLD_INT_MASK_REG);
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__raw_writew(0xFFFF, CPLD_INT_RESET_REG);
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__raw_writew(0, CPLD_INT_RESET_REG);
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__raw_writew(0x1F, CPLD_INT_MASK_REG);
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for (i = MXC_EXP_IO_BASE;
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i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
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i++) {
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set_irq_chip(i, &expio_irq_chip);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
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set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
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return 0;
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}
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/*
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* This structure defines the MX31 memory map.
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*/
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static struct map_desc mx31_3ds_io_desc[] __initdata = {
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{
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.virtual = MX31_CS5_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
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.length = MX31_CS5_SIZE,
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.type = MT_DEVICE,
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},
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};
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/*
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* Set up static virtual mappings.
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*/
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static void __init mx31_3ds_map_io(void)
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{
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mx31_map_io();
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iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
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}
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/*!
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* Board specific initialization.
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*/
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static void __init mxc_board_init(void)
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{
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mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
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"mx31_3ds");
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mxc_register_device(&mxc_uart_device0, &uart_pdata);
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mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
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mxc_register_device(&mxc_spi_device1, &spi1_pdata);
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spi_register_board_info(mx31_3ds_spi_devs,
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ARRAY_SIZE(mx31_3ds_spi_devs));
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if (!mx31_3ds_init_expio())
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platform_device_register(&smsc911x_device);
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}
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static void __init mx31_3ds_timer_init(void)
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{
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mx31_clocks_init(26000000);
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}
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static struct sys_timer mx31_3ds_timer = {
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.init = mx31_3ds_timer_init,
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};
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/*
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* The following uses standard kernel macros defined in arch.h in order to
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* initialize __mach_desc_MX31_3DS data structure.
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*/
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MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
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/* Maintainer: Freescale Semiconductor, Inc. */
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.phys_io = MX31_AIPS1_BASE_ADDR,
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.io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
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.boot_params = MX3x_PHYS_OFFSET + 0x100,
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.map_io = mx31_3ds_map_io,
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.init_irq = mx31_init_irq,
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.init_machine = mxc_board_init,
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.timer = &mx31_3ds_timer,
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MACHINE_END
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