forked from luck/tmp_suning_uos_patched
bec0806cfe
Add pseudo-DMA by FIQ to the S3C24XX SPI driver. This allows the driver to get DMA-like performance where there are either no free DMA channels or when doing transfers that required both TX and RX data paths. Since this patch requires the addition of an assembly file to hold the FIQ code, we rename the module (instead of adding a rename of the .c file to this patch). We expect most users are loading this via udev and thus there should be no change to the userland configuration. Signed-off-by: Ben Dooks <ben@simtec.co.uk> Signed-off-by: Simtec Linux Team <linux@simtec.co.uk> Cc: David Brownell <david-b@pacbell.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
39 lines
1.1 KiB
C
39 lines
1.1 KiB
C
/* arch/arm/mach-s3c2410/include/mach/spi.h
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*
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2410 - SPI Controller platform_device info
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_SPI_H
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#define __ASM_ARCH_SPI_H __FILE__
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struct s3c2410_spi_info {
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int pin_cs; /* simple gpio cs */
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unsigned int num_cs; /* total chipselects */
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int bus_num; /* bus number to use. */
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unsigned int use_fiq:1; /* use fiq */
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void (*gpio_setup)(struct s3c2410_spi_info *spi, int enable);
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void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
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};
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/* Standard setup / suspend routines for SPI GPIO pins. */
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extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
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int enable);
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extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
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int enable);
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extern void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
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int enable);
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#endif /* __ASM_ARCH_SPI_H */
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