forked from luck/tmp_suning_uos_patched
b2edcfc814
Loongson-3 CPU family:
Code-name Brand-name PRId
Loongson-3A R1 Loongson-3A1000 0x6305
Loongson-3A R2 Loongson-3A2000 0x6308
Loongson-3B R1 Loongson-3B1000 0x6306
Loongson-3B R2 Loongson-3B1500 0x6307
Features of R2 revision of Loongson-3A:
- Primary cache includes I-Cache, D-Cache and V-Cache (Victim Cache).
- I-Cache, D-Cache and V-Cache are 16-way set-associative, linesize is
64 bytes.
- 64 entries of VTLB (classic TLB), 1024 entries of FTLB (8-way
set-associative).
- Supports DSP/DSPv2 instructions, UserLocal register and Read-Inhibit/
Execute-Inhibit.
[ralf@linux-mips.org: Resolved merge conflicts.]
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12751/
Patchwork: https://patchwork.linux-mips.org/patch/13136/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
274 lines
6.0 KiB
C
274 lines
6.0 KiB
C
/*
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* MIPS idle loop and WAIT instruction support.
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*
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* Copyright (C) xxxx the Anonymous
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* Copyright (C) 1994 - 2006 Ralf Baechle
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* Copyright (C) 2003, 2004 Maciej W. Rozycki
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* Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/irqflags.h>
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#include <linux/printk.h>
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#include <linux/sched.h>
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#include <asm/cpu.h>
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#include <asm/cpu-info.h>
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#include <asm/cpu-type.h>
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#include <asm/idle.h>
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#include <asm/mipsregs.h>
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/*
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* Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
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* the implementation of the "wait" feature differs between CPU families. This
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* points to the function that implements CPU specific wait.
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* The wait instruction stops the pipeline and reduces the power consumption of
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* the CPU very much.
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*/
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void (*cpu_wait)(void);
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EXPORT_SYMBOL(cpu_wait);
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static void r3081_wait(void)
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{
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unsigned long cfg = read_c0_conf();
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write_c0_conf(cfg | R30XX_CONF_HALT);
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local_irq_enable();
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}
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static void r39xx_wait(void)
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{
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if (!need_resched())
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write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
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local_irq_enable();
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}
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void r4k_wait(void)
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{
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local_irq_enable();
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__r4k_wait();
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}
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/*
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* This variant is preferable as it allows testing need_resched and going to
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* sleep depending on the outcome atomically. Unfortunately the "It is
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* implementation-dependent whether the pipeline restarts when a non-enabled
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* interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
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* using this version a gamble.
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*/
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void r4k_wait_irqoff(void)
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{
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if (!need_resched())
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__asm__(
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" .set push \n"
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" .set arch=r4000 \n"
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" wait \n"
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" .set pop \n");
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local_irq_enable();
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}
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/*
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* The RM7000 variant has to handle erratum 38. The workaround is to not
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* have any pending stores when the WAIT instruction is executed.
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*/
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static void rm7k_wait_irqoff(void)
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{
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if (!need_resched())
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__asm__(
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" .set push \n"
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" .set arch=r4000 \n"
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" .set noat \n"
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" mfc0 $1, $12 \n"
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" sync \n"
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" mtc0 $1, $12 # stalls until W stage \n"
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" wait \n"
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" mtc0 $1, $12 # stalls until W stage \n"
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" .set pop \n");
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local_irq_enable();
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}
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/*
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* Au1 'wait' is only useful when the 32kHz counter is used as timer,
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* since coreclock (and the cp0 counter) stops upon executing it. Only an
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* interrupt can wake it, so they must be enabled before entering idle modes.
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*/
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static void au1k_wait(void)
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{
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unsigned long c0status = read_c0_status() | 1; /* irqs on */
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__asm__(
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" .set arch=r4000 \n"
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" cache 0x14, 0(%0) \n"
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" cache 0x14, 32(%0) \n"
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" sync \n"
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" mtc0 %1, $12 \n" /* wr c0status */
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" wait \n"
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" nop \n"
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" nop \n"
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" nop \n"
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" nop \n"
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" .set mips0 \n"
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: : "r" (au1k_wait), "r" (c0status));
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}
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static int __initdata nowait;
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static int __init wait_disable(char *s)
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{
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nowait = 1;
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return 1;
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}
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__setup("nowait", wait_disable);
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void __init check_wait(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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if (nowait) {
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printk("Wait instruction disabled.\n");
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return;
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}
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/*
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* MIPSr6 specifies that masked interrupts should unblock an executing
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* wait instruction, and thus that it is safe for us to use
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* r4k_wait_irqoff. Yippee!
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*/
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if (cpu_has_mips_r6) {
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cpu_wait = r4k_wait_irqoff;
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return;
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}
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switch (current_cpu_type()) {
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case CPU_R3081:
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case CPU_R3081E:
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cpu_wait = r3081_wait;
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break;
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case CPU_TX3927:
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cpu_wait = r39xx_wait;
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break;
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case CPU_R4200:
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/* case CPU_R4300: */
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case CPU_R4600:
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case CPU_R4640:
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case CPU_R4650:
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case CPU_R4700:
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case CPU_R5000:
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case CPU_R5500:
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case CPU_NEVADA:
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case CPU_4KC:
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case CPU_4KEC:
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case CPU_4KSC:
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case CPU_5KC:
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case CPU_5KE:
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case CPU_25KF:
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case CPU_PR4450:
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case CPU_BMIPS3300:
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case CPU_BMIPS4350:
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case CPU_BMIPS4380:
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case CPU_CAVIUM_OCTEON:
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case CPU_CAVIUM_OCTEON_PLUS:
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case CPU_CAVIUM_OCTEON2:
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case CPU_CAVIUM_OCTEON3:
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case CPU_JZRISC:
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case CPU_LOONGSON1:
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case CPU_XLR:
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case CPU_XLP:
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cpu_wait = r4k_wait;
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break;
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case CPU_LOONGSON3:
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if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2)
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cpu_wait = r4k_wait;
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break;
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case CPU_BMIPS5000:
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cpu_wait = r4k_wait_irqoff;
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break;
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case CPU_RM7000:
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cpu_wait = rm7k_wait_irqoff;
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break;
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case CPU_PROAPTIV:
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case CPU_P5600:
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/*
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* Incoming Fast Debug Channel (FDC) data during a wait
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* instruction causes the wait never to resume, even if an
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* interrupt is received. Avoid using wait at all if FDC data is
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* likely to be received.
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*/
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if (IS_ENABLED(CONFIG_MIPS_EJTAG_FDC_TTY))
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break;
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/* fall through */
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case CPU_M14KC:
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case CPU_M14KEC:
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case CPU_24K:
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case CPU_34K:
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case CPU_1004K:
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case CPU_1074K:
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case CPU_INTERAPTIV:
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case CPU_M5150:
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case CPU_QEMU_GENERIC:
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cpu_wait = r4k_wait;
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if (read_c0_config7() & MIPS_CONF7_WII)
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cpu_wait = r4k_wait_irqoff;
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break;
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case CPU_74K:
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cpu_wait = r4k_wait;
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if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
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cpu_wait = r4k_wait_irqoff;
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break;
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case CPU_TX49XX:
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cpu_wait = r4k_wait_irqoff;
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break;
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case CPU_ALCHEMY:
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cpu_wait = au1k_wait;
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break;
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case CPU_20KC:
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/*
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* WAIT on Rev1.0 has E1, E2, E3 and E16.
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* WAIT on Rev2.0 and Rev3.0 has E16.
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* Rev3.1 WAIT is nop, why bother
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*/
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if ((c->processor_id & 0xff) <= 0x64)
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break;
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/*
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* Another rev is incremeting c0_count at a reduced clock
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* rate while in WAIT mode. So we basically have the choice
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* between using the cp0 timer as clocksource or avoiding
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* the WAIT instruction. Until more details are known,
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* disable the use of WAIT for 20Kc entirely.
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cpu_wait = r4k_wait;
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*/
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break;
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default:
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break;
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}
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}
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void arch_cpu_idle(void)
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{
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if (cpu_wait)
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cpu_wait();
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else
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local_irq_enable();
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}
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#ifdef CONFIG_CPU_IDLE
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int mips_cpuidle_wait_enter(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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arch_cpu_idle();
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return index;
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}
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#endif
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