forked from luck/tmp_suning_uos_patched
b633648c5a
Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras <Markos.Chandras@imgtec.com> patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
166 lines
4.2 KiB
C
166 lines
4.2 KiB
C
/*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Copyright (C) 2007 MIPS Technologies, Inc.
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* Chris Dearman (chris@mips.com)
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/cpumask.h>
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#include <linux/interrupt.h>
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#include <linux/compiler.h>
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#include <linux/atomic.h>
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#include <asm/cacheflush.h>
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#include <asm/cpu.h>
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#include <asm/processor.h>
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#include <asm/hardirq.h>
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#include <asm/mmu_context.h>
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#include <asm/smp.h>
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#include <asm/time.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/mips_mt.h>
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#include <asm/amon.h>
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#include <asm/gic.h>
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static void cmp_init_secondary(void)
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{
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struct cpuinfo_mips *c __maybe_unused = ¤t_cpu_data;
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/* Assume GIC is present */
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change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 |
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STATUSF_IP7);
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/* Enable per-cpu interrupts: platform specific */
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#ifdef CONFIG_MIPS_MT_SMP
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if (cpu_has_mipsmt)
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c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
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TCBIND_CURVPE;
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#endif
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}
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static void cmp_smp_finish(void)
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{
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pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
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/* CDFIXME: remove this? */
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write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
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#ifdef CONFIG_MIPS_MT_FPAFF
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/* If we have an FPU, enroll ourselves in the FPU-full mask */
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if (cpu_has_fpu)
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cpu_set(smp_processor_id(), mt_fpu_cpumask);
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#endif /* CONFIG_MIPS_MT_FPAFF */
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local_irq_enable();
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}
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static void cmp_cpus_done(void)
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{
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pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
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}
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/*
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* Setup the PC, SP, and GP of a secondary processor and start it running
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* smp_bootstrap is the place to resume from
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* __KSTK_TOS(idle) is apparently the stack pointer
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* (unsigned long)idle->thread_info the gp
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*/
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static void cmp_boot_secondary(int cpu, struct task_struct *idle)
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{
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struct thread_info *gp = task_thread_info(idle);
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unsigned long sp = __KSTK_TOS(idle);
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unsigned long pc = (unsigned long)&smp_bootstrap;
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unsigned long a0 = 0;
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pr_debug("SMPCMP: CPU%d: %s cpu %d\n", smp_processor_id(),
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__func__, cpu);
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#if 0
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/* Needed? */
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flush_icache_range((unsigned long)gp,
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(unsigned long)(gp + sizeof(struct thread_info)));
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#endif
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amon_cpu_start(cpu, pc, sp, (unsigned long)gp, a0);
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}
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/*
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* Common setup before any secondaries are started
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*/
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void __init cmp_smp_setup(void)
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{
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int i;
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int ncpu = 0;
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pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
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#ifdef CONFIG_MIPS_MT_FPAFF
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/* If we have an FPU, enroll ourselves in the FPU-full mask */
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if (cpu_has_fpu)
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cpu_set(0, mt_fpu_cpumask);
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#endif /* CONFIG_MIPS_MT_FPAFF */
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for (i = 1; i < NR_CPUS; i++) {
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if (amon_cpu_avail(i)) {
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set_cpu_possible(i, true);
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__cpu_number_map[i] = ++ncpu;
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__cpu_logical_map[ncpu] = i;
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}
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}
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if (cpu_has_mipsmt) {
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unsigned int nvpe = 1;
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#ifdef CONFIG_MIPS_MT_SMP
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unsigned int mvpconf0 = read_c0_mvpconf0();
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nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
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#endif
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smp_num_siblings = nvpe;
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}
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pr_info("Detected %i available secondary CPU(s)\n", ncpu);
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}
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void __init cmp_prepare_cpus(unsigned int max_cpus)
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{
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pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n",
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smp_processor_id(), __func__, max_cpus);
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#ifdef CONFIG_MIPS_MT
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/*
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* FIXME: some of these options are per-system, some per-core and
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* some per-cpu
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*/
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mips_mt_set_cpuoptions();
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#endif
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}
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struct plat_smp_ops cmp_smp_ops = {
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.send_ipi_single = gic_send_ipi_single,
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.send_ipi_mask = gic_send_ipi_mask,
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.init_secondary = cmp_init_secondary,
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.smp_finish = cmp_smp_finish,
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.cpus_done = cmp_cpus_done,
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.boot_secondary = cmp_boot_secondary,
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.smp_setup = cmp_smp_setup,
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.prepare_cpus = cmp_prepare_cpus,
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};
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