forked from luck/tmp_suning_uos_patched
b70eb30056
Implement 1 & 2 byte xchg() using read-modify-write atop a 4 byte cmpxchg(). This allows us to support these atomic operations despite the MIPS ISA only providing for 4 & 8 byte atomic operations. This is required in order to support queued spinlocks (qspinlock) in a later patch, since these make use of a 2 byte xchg() in their slow path. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16354/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
/*
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* Copyright (C) 2017 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/bitops.h>
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#include <asm/cmpxchg.h>
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unsigned long __xchg_small(volatile void *ptr, unsigned long val, unsigned int size)
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{
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u32 old32, new32, load32, mask;
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volatile u32 *ptr32;
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unsigned int shift;
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/* Check that ptr is naturally aligned */
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WARN_ON((unsigned long)ptr & (size - 1));
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/* Mask value to the correct size. */
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mask = GENMASK((size * BITS_PER_BYTE) - 1, 0);
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val &= mask;
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/*
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* Calculate a shift & mask that correspond to the value we wish to
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* exchange within the naturally aligned 4 byte integerthat includes
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* it.
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*/
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shift = (unsigned long)ptr & 0x3;
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if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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shift ^= sizeof(u32) - size;
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shift *= BITS_PER_BYTE;
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mask <<= shift;
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/*
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* Calculate a pointer to the naturally aligned 4 byte integer that
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* includes our byte of interest, and load its value.
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*/
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ptr32 = (volatile u32 *)((unsigned long)ptr & ~0x3);
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load32 = *ptr32;
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do {
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old32 = load32;
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new32 = (load32 & ~mask) | (val << shift);
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load32 = cmpxchg(ptr32, old32, new32);
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} while (load32 != old32);
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return (load32 & mask) >> shift;
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}
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