forked from luck/tmp_suning_uos_patched
59904159c3
a) update entry in CREDITS for Jesper Juhl b) remove email address from source files so it's only listed in credits. Signed-off-by: Jesper Juhl <jesper.juhl@gmail.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
370 lines
11 KiB
C
370 lines
11 KiB
C
/*
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* linux/drivers/ide/pci/trm290.c Version 1.02 Mar. 18, 2000
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*
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* Copyright (c) 1997-1998 Mark Lord
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* May be copied or modified under the terms of the GNU General Public License
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*
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* June 22, 2004 - get rid of check_region
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* - Jesper Juhl
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*
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*/
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/*
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* This module provides support for the bus-master IDE DMA function
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* of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
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* including a "Precision Instruments" board. The TRM290 pre-dates
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* the sff-8038 standard (ide-dma.c) by a few months, and differs
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* significantly enough to warrant separate routines for some functions,
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* while re-using others from ide-dma.c.
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*
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* EXPERIMENTAL! It works for me (a sample of one).
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*
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* Works reliably for me in DMA mode (READs only),
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* DMA WRITEs are disabled by default (see #define below);
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*
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* DMA is not enabled automatically for this chipset,
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* but can be turned on manually (with "hdparm -d1") at run time.
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*
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* I need volunteers with "spare" drives for further testing
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* and development, and maybe to help figure out the peculiarities.
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* Even knowing the registers (below), some things behave strangely.
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*/
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#define TRM290_NO_DMA_WRITES /* DMA writes seem unreliable sometimes */
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/*
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* TRM-290 PCI-IDE2 Bus Master Chip
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* ================================
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* The configuration registers are addressed in normal I/O port space
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* and are used as follows:
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*
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* trm290_base depends on jumper settings, and is probed for by ide-dma.c
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*
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* trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
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* bit7 must always be written as "1"
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* bits6-2 undefined
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* bit1 1=legacy_compatible_mode, 0=native_pci_mode
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* bit0 1=test_mode, 0=normal(default)
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*
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* trm290_base+2 when READ: status register (byte, read-only)
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* bits7-2 undefined
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* bit1 channel0 busmaster interrupt status 0=none, 1=asserted
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* bit0 channel0 interrupt status 0=none, 1=asserted
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*
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* trm290_base+3 Interrupt mask register
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* bits7-5 undefined
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* bit4 legacy_header: 1=present, 0=absent
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* bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
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* bit2 channel1 interrupt status 0=none, 1=asserted (read only)
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* bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
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* bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
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*
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* trm290_base+1 "CPR" Config Pointer Register (byte)
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* bit7 1=autoincrement CPR bits 2-0 after each access of CDR
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* bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
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* bit5 0=enabled master burst access (default), 1=disable (write only)
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* bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
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* bit3 0=primary IDE channel, 1=secondary IDE channel
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* bits2-0 register index for accesses through CDR port
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*
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* trm290_base+0 "CDR" Config Data Register (word)
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* two sets of seven config registers,
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* selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
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* each index defined below:
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*
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* Index-0 Base address register for command block (word)
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* defaults: 0x1f0 for primary, 0x170 for secondary
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*
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* Index-1 general config register (byte)
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* bit7 1=DMA enable, 0=DMA disable
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* bit6 1=activate IDE_RESET, 0=no action (default)
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* bit5 1=enable IORDY, 0=disable IORDY (default)
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* bit4 0=16-bit data port(default), 1=8-bit (XT) data port
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* bit3 interrupt polarity: 1=active_low, 0=active_high(default)
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* bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
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* bit1 bus_master_mode(?): 1=enable, 0=disable(default)
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* bit0 enable_io_ports: 1=enable(default), 0=disable
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*
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* Index-2 read-ahead counter preload bits 0-7 (byte, write only)
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* bits7-0 bits7-0 of readahead count
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*
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* Index-3 read-ahead config register (byte, write only)
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* bit7 1=enable_readahead, 0=disable_readahead(default)
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* bit6 1=clear_FIFO, 0=no_action
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* bit5 undefined
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* bit4 mode4 timing control: 1=enable, 0=disable(default)
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* bit3 undefined
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* bit2 undefined
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* bits1-0 bits9-8 of read-ahead count
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*
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* Index-4 base address register for control block (word)
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* defaults: 0x3f6 for primary, 0x376 for secondary
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*
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* Index-5 data port timings (shared by both drives) (byte)
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* standard PCI "clk" (clock) counts, default value = 0xf5
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*
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* bits7-6 setup time: 00=1clk, 01=2clk, 10=3clk, 11=4clk
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* bits5-3 hold time: 000=1clk, 001=2clk, 010=3clk,
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* 011=4clk, 100=5clk, 101=6clk,
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* 110=8clk, 111=12clk
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* bits2-0 active time: 000=2clk, 001=3clk, 010=4clk,
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* 011=5clk, 100=6clk, 101=8clk,
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* 110=12clk, 111=16clk
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*
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* Index-6 command/control port timings (shared by both drives) (byte)
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* same layout as Index-5, default value = 0xde
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*
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* Suggested CDR programming for PIO mode0 (600ns):
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* 0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde ; primary
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* 0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde ; secondary
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*
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* Suggested CDR programming for PIO mode3 (180ns):
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* 0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde ; primary
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* 0x0170,0x21,0xff,0x80,0x0376,0x09,0xde ; secondary
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*
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* Suggested CDR programming for PIO mode4 (120ns):
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* 0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde ; primary
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* 0x0170,0x21,0xff,0x80,0x0376,0x00,0xde ; secondary
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*
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/blkdev.h>
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#include <linux/init.h>
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#include <linux/hdreg.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/ide.h>
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#include <asm/io.h>
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static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
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{
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ide_hwif_t *hwif = HWIF(drive);
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u16 reg = 0;
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unsigned long flags;
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/* select PIO or DMA */
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reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);
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local_irq_save(flags);
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if (reg != hwif->select_data) {
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hwif->select_data = reg;
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/* set PIO/DMA */
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hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
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hwif->OUTW(reg & 0xff, hwif->config_data);
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}
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/* enable IRQ if not probing */
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if (drive->present) {
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reg = hwif->INW(hwif->config_data + 3);
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reg &= 0x13;
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reg &= ~(1 << hwif->channel);
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hwif->OUTW(reg, hwif->config_data+3);
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}
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local_irq_restore(flags);
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}
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static void trm290_selectproc (ide_drive_t *drive)
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{
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trm290_prepare_drive(drive, drive->using_dma);
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}
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#ifdef CONFIG_BLK_DEV_IDEDMA
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static void trm290_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
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{
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ide_hwif_t *hwif = HWIF(drive);
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if (HWGROUP(drive)->handler != NULL) /* paranoia check */
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BUG();
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ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
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/* issue cmd to drive */
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hwif->OUTB(command, IDE_COMMAND_REG);
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}
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static int trm290_ide_dma_setup(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct request *rq = hwif->hwgroup->rq;
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unsigned int count, rw;
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if (rq_data_dir(rq)) {
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#ifdef TRM290_NO_DMA_WRITES
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/* always use PIO for writes */
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trm290_prepare_drive(drive, 0); /* select PIO xfer */
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return 1;
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#endif
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rw = 1;
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} else
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rw = 2;
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if (!(count = ide_build_dmatable(drive, rq))) {
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/* try PIO instead of DMA */
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trm290_prepare_drive(drive, 0); /* select PIO xfer */
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return 1;
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}
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/* select DMA xfer */
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trm290_prepare_drive(drive, 1);
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hwif->OUTL(hwif->dmatable_dma|rw, hwif->dma_command);
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drive->waiting_for_dma = 1;
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/* start DMA */
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hwif->OUTW((count * 2) - 1, hwif->dma_status);
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return 0;
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}
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static void trm290_ide_dma_start(ide_drive_t *drive)
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{
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}
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static int trm290_ide_dma_end (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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u16 status = 0;
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drive->waiting_for_dma = 0;
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/* purge DMA mappings */
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ide_destroy_dmatable(drive);
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status = hwif->INW(hwif->dma_status);
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return (status != 0x00ff);
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}
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static int trm290_ide_dma_test_irq (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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u16 status = 0;
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status = hwif->INW(hwif->dma_status);
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return (status == 0x00ff);
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}
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#endif /* CONFIG_BLK_DEV_IDEDMA */
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/*
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* Invoked from ide-dma.c at boot time.
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*/
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static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
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{
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unsigned int cfgbase = 0;
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unsigned long flags;
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u8 reg = 0;
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struct pci_dev *dev = hwif->pci_dev;
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hwif->no_lba48 = 1;
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hwif->chipset = ide_trm290;
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cfgbase = pci_resource_start(dev, 4);
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if ((dev->class & 5) && cfgbase) {
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hwif->config_data = cfgbase;
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printk(KERN_INFO "TRM290: chip config base at 0x%04lx\n",
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hwif->config_data);
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} else {
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hwif->config_data = 0x3df0;
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printk(KERN_INFO "TRM290: using default config base at 0x%04lx\n",
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hwif->config_data);
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}
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local_irq_save(flags);
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/* put config reg into first byte of hwif->select_data */
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hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
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/* select PIO as default */
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hwif->select_data = 0x21;
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hwif->OUTB(hwif->select_data, hwif->config_data);
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/* get IRQ info */
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reg = hwif->INB(hwif->config_data+3);
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/* mask IRQs for both ports */
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reg = (reg & 0x10) | 0x03;
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hwif->OUTB(reg, hwif->config_data+3);
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local_irq_restore(flags);
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if ((reg & 0x10))
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/* legacy mode */
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hwif->irq = hwif->channel ? 15 : 14;
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else if (!hwif->irq && hwif->mate && hwif->mate->irq)
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/* sharing IRQ with mate */
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hwif->irq = hwif->mate->irq;
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ide_setup_dma(hwif, (hwif->config_data + 4) ^ (hwif->channel ? 0x0080 : 0x0000), 3);
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#ifdef CONFIG_BLK_DEV_IDEDMA
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hwif->dma_setup = &trm290_ide_dma_setup;
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hwif->dma_exec_cmd = &trm290_ide_dma_exec_cmd;
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hwif->dma_start = &trm290_ide_dma_start;
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hwif->ide_dma_end = &trm290_ide_dma_end;
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hwif->ide_dma_test_irq = &trm290_ide_dma_test_irq;
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#endif /* CONFIG_BLK_DEV_IDEDMA */
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hwif->selectproc = &trm290_selectproc;
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hwif->autodma = 0; /* play it safe for now */
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hwif->drives[0].autodma = hwif->autodma;
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hwif->drives[1].autodma = hwif->autodma;
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#if 1
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{
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/*
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* My trm290-based card doesn't seem to work with all possible values
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* for the control basereg, so this kludge ensures that we use only
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* values that are known to work. Ugh. -ml
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*/
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u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;
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static u16 next_offset = 0;
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u8 old_mask;
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hwif->OUTB(0x54|(hwif->channel<<3), hwif->config_data+1);
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old = hwif->INW(hwif->config_data);
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old &= ~1;
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old_mask = hwif->INB(old+2);
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if (old != compat && old_mask == 0xff) {
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/* leave lower 10 bits untouched */
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compat += (next_offset += 0x400);
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hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2;
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hwif->OUTW(compat|1, hwif->config_data);
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new = hwif->INW(hwif->config_data);
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printk(KERN_INFO "%s: control basereg workaround: "
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"old=0x%04x, new=0x%04x\n",
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hwif->name, old, new & ~1);
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}
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}
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#endif
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}
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static ide_pci_device_t trm290_chipset __devinitdata = {
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.name = "TRM290",
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.init_hwif = init_hwif_trm290,
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.channels = 2,
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.autodma = NOAUTODMA,
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.bootable = ON_BOARD,
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};
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static int __devinit trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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return ide_setup_pci_device(dev, &trm290_chipset);
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}
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static struct pci_device_id trm290_pci_tbl[] = {
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{ PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, trm290_pci_tbl);
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static struct pci_driver driver = {
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.name = "TRM290_IDE",
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.id_table = trm290_pci_tbl,
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.probe = trm290_init_one,
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};
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static int trm290_ide_init(void)
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{
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return ide_pci_register_driver(&driver);
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}
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module_init(trm290_ide_init);
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MODULE_AUTHOR("Mark Lord");
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MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE");
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MODULE_LICENSE("GPL");
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