forked from luck/tmp_suning_uos_patched
9832bf3a35
* pm-cpufreq: Revert "Documentation: kernel_parameters for Intel P state driver" cpufreq: mediatek: fix build error cpufreq: intel_pstate: Add separate support for Airmont cores cpufreq: intel_pstate: Replace BYT with ATOM Revert "cpufreq: intel_pstate: Use ACPI perf configuration" Revert "cpufreq: intel_pstate: Avoid calculation for max/min" * acpi-cppc: ACPI / CPPC: Use h/w reduced version of the PCCT structure
734 lines
19 KiB
C
734 lines
19 KiB
C
/*
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* CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
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*
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* (C) Copyright 2014, 2015 Linaro Ltd.
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* Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*
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* CPPC describes a few methods for controlling CPU performance using
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* information from a per CPU table called CPC. This table is described in
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* the ACPI v5.0+ specification. The table consists of a list of
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* registers which may be memory mapped or hardware registers and also may
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* include some static integer values.
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*
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* CPU performance is on an abstract continuous scale as against a discretized
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* P-state scale which is tied to CPU frequency only. In brief, the basic
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* operation involves:
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*
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* - OS makes a CPU performance request. (Can provide min and max bounds)
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*
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* - Platform (such as BMC) is free to optimize request within requested bounds
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* depending on power/thermal budgets etc.
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*
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* - Platform conveys its decision back to OS
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*
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* The communication between OS and platform occurs through another medium
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* called (PCC) Platform Communication Channel. This is a generic mailbox like
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* mechanism which includes doorbell semantics to indicate register updates.
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* See drivers/mailbox/pcc.c for details on PCC.
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*
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* Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
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* above specifications.
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*/
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#define pr_fmt(fmt) "ACPI CPPC: " fmt
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#include <linux/cpufreq.h>
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#include <linux/delay.h>
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#include <acpi/cppc_acpi.h>
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/*
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* Lock to provide mutually exclusive access to the PCC
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* channel. e.g. When the remote updates the shared region
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* with new data, the reader needs to be protected from
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* other CPUs activity on the same channel.
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*/
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static DEFINE_SPINLOCK(pcc_lock);
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/*
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* The cpc_desc structure contains the ACPI register details
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* as described in the per CPU _CPC tables. The details
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* include the type of register (e.g. PCC, System IO, FFH etc.)
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* and destination addresses which lets us READ/WRITE CPU performance
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* information using the appropriate I/O methods.
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*/
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static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
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/* This layer handles all the PCC specifics for CPPC. */
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static struct mbox_chan *pcc_channel;
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static void __iomem *pcc_comm_addr;
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static u64 comm_base_addr;
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static int pcc_subspace_idx = -1;
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static u16 pcc_cmd_delay;
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static bool pcc_channel_acquired;
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/*
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* Arbitrary Retries in case the remote processor is slow to respond
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* to PCC commands.
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*/
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#define NUM_RETRIES 500
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static int send_pcc_cmd(u16 cmd)
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{
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int retries, result = -EIO;
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struct acpi_pcct_hw_reduced *pcct_ss = pcc_channel->con_priv;
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struct acpi_pcct_shared_memory *generic_comm_base =
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(struct acpi_pcct_shared_memory *) pcc_comm_addr;
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u32 cmd_latency = pcct_ss->latency;
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/* Min time OS should wait before sending next command. */
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udelay(pcc_cmd_delay);
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/* Write to the shared comm region. */
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writew(cmd, &generic_comm_base->command);
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/* Flip CMD COMPLETE bit */
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writew(0, &generic_comm_base->status);
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/* Ring doorbell */
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result = mbox_send_message(pcc_channel, &cmd);
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if (result < 0) {
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pr_err("Err sending PCC mbox message. cmd:%d, ret:%d\n",
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cmd, result);
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return result;
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}
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/* Wait for a nominal time to let platform process command. */
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udelay(cmd_latency);
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/* Retry in case the remote processor was too slow to catch up. */
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for (retries = NUM_RETRIES; retries > 0; retries--) {
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if (readw_relaxed(&generic_comm_base->status) & PCC_CMD_COMPLETE) {
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result = 0;
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break;
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}
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}
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mbox_client_txdone(pcc_channel, result);
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return result;
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}
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static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
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{
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if (ret)
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pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
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*(u16 *)msg, ret);
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else
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pr_debug("TX completed. CMD sent:%x, ret:%d\n",
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*(u16 *)msg, ret);
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}
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struct mbox_client cppc_mbox_cl = {
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.tx_done = cppc_chan_tx_done,
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.knows_txdone = true,
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};
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static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
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{
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int result = -EFAULT;
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acpi_status status = AE_OK;
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struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
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struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
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struct acpi_buffer state = {0, NULL};
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union acpi_object *psd = NULL;
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struct acpi_psd_package *pdomain;
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status = acpi_evaluate_object_typed(handle, "_PSD", NULL, &buffer,
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ACPI_TYPE_PACKAGE);
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if (ACPI_FAILURE(status))
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return -ENODEV;
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psd = buffer.pointer;
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if (!psd || psd->package.count != 1) {
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pr_debug("Invalid _PSD data\n");
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goto end;
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}
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pdomain = &(cpc_ptr->domain_info);
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state.length = sizeof(struct acpi_psd_package);
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state.pointer = pdomain;
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status = acpi_extract_package(&(psd->package.elements[0]),
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&format, &state);
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if (ACPI_FAILURE(status)) {
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pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
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goto end;
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}
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if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
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pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
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goto end;
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}
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if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
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pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
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goto end;
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}
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if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
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pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
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pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
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pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
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goto end;
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}
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result = 0;
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end:
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kfree(buffer.pointer);
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return result;
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}
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/**
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* acpi_get_psd_map - Map the CPUs in a common freq domain.
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* @all_cpu_data: Ptrs to CPU specific CPPC data including PSD info.
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*
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* Return: 0 for success or negative value for err.
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*/
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int acpi_get_psd_map(struct cpudata **all_cpu_data)
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{
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int count_target;
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int retval = 0;
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unsigned int i, j;
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cpumask_var_t covered_cpus;
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struct cpudata *pr, *match_pr;
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struct acpi_psd_package *pdomain;
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struct acpi_psd_package *match_pdomain;
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struct cpc_desc *cpc_ptr, *match_cpc_ptr;
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if (!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL))
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return -ENOMEM;
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/*
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* Now that we have _PSD data from all CPUs, lets setup P-state
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* domain info.
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*/
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for_each_possible_cpu(i) {
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pr = all_cpu_data[i];
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if (!pr)
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continue;
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if (cpumask_test_cpu(i, covered_cpus))
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continue;
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cpc_ptr = per_cpu(cpc_desc_ptr, i);
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if (!cpc_ptr)
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continue;
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pdomain = &(cpc_ptr->domain_info);
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cpumask_set_cpu(i, pr->shared_cpu_map);
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cpumask_set_cpu(i, covered_cpus);
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if (pdomain->num_processors <= 1)
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continue;
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/* Validate the Domain info */
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count_target = pdomain->num_processors;
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if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
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pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
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else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
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pr->shared_type = CPUFREQ_SHARED_TYPE_HW;
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else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
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pr->shared_type = CPUFREQ_SHARED_TYPE_ANY;
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for_each_possible_cpu(j) {
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if (i == j)
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continue;
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match_cpc_ptr = per_cpu(cpc_desc_ptr, j);
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if (!match_cpc_ptr)
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continue;
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match_pdomain = &(match_cpc_ptr->domain_info);
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if (match_pdomain->domain != pdomain->domain)
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continue;
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/* Here i and j are in the same domain */
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if (match_pdomain->num_processors != count_target) {
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retval = -EFAULT;
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goto err_ret;
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}
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if (pdomain->coord_type != match_pdomain->coord_type) {
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retval = -EFAULT;
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goto err_ret;
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}
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cpumask_set_cpu(j, covered_cpus);
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cpumask_set_cpu(j, pr->shared_cpu_map);
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}
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for_each_possible_cpu(j) {
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if (i == j)
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continue;
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match_pr = all_cpu_data[j];
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if (!match_pr)
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continue;
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match_cpc_ptr = per_cpu(cpc_desc_ptr, j);
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if (!match_cpc_ptr)
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continue;
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match_pdomain = &(match_cpc_ptr->domain_info);
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if (match_pdomain->domain != pdomain->domain)
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continue;
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match_pr->shared_type = pr->shared_type;
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cpumask_copy(match_pr->shared_cpu_map,
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pr->shared_cpu_map);
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}
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}
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err_ret:
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for_each_possible_cpu(i) {
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pr = all_cpu_data[i];
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if (!pr)
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continue;
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/* Assume no coordination on any error parsing domain info */
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if (retval) {
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cpumask_clear(pr->shared_cpu_map);
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cpumask_set_cpu(i, pr->shared_cpu_map);
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pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
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}
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}
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free_cpumask_var(covered_cpus);
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return retval;
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}
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EXPORT_SYMBOL_GPL(acpi_get_psd_map);
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static int register_pcc_channel(int pcc_subspace_idx)
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{
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struct acpi_pcct_hw_reduced *cppc_ss;
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unsigned int len;
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if (pcc_subspace_idx >= 0) {
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pcc_channel = pcc_mbox_request_channel(&cppc_mbox_cl,
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pcc_subspace_idx);
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if (IS_ERR(pcc_channel)) {
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pr_err("Failed to find PCC communication channel\n");
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return -ENODEV;
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}
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/*
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* The PCC mailbox controller driver should
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* have parsed the PCCT (global table of all
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* PCC channels) and stored pointers to the
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* subspace communication region in con_priv.
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*/
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cppc_ss = pcc_channel->con_priv;
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if (!cppc_ss) {
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pr_err("No PCC subspace found for CPPC\n");
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return -ENODEV;
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}
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/*
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* This is the shared communication region
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* for the OS and Platform to communicate over.
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*/
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comm_base_addr = cppc_ss->base_address;
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len = cppc_ss->length;
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pcc_cmd_delay = cppc_ss->min_turnaround_time;
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pcc_comm_addr = acpi_os_ioremap(comm_base_addr, len);
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if (!pcc_comm_addr) {
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pr_err("Failed to ioremap PCC comm region mem\n");
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return -ENOMEM;
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}
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|
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/* Set flag so that we dont come here for each CPU. */
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pcc_channel_acquired = true;
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}
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return 0;
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}
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|
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/*
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* An example CPC table looks like the following.
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*
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* Name(_CPC, Package()
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* {
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* 17,
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* NumEntries
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* 1,
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* // Revision
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* ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)},
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* // Highest Performance
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* ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)},
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* // Nominal Performance
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* ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)},
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* // Lowest Nonlinear Performance
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* ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)},
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* // Lowest Performance
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* ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)},
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* // Guaranteed Performance Register
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* ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)},
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* // Desired Performance Register
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* ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)},
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* ..
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* ..
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* ..
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*
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* }
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* Each Register() encodes how to access that specific register.
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* e.g. a sample PCC entry has the following encoding:
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*
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* Register (
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* PCC,
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* AddressSpaceKeyword
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* 8,
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* //RegisterBitWidth
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* 8,
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* //RegisterBitOffset
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* 0x30,
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* //RegisterAddress
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* 9
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* //AccessSize (subspace ID)
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* 0
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* )
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* }
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*/
|
|
|
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/**
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* acpi_cppc_processor_probe - Search for per CPU _CPC objects.
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* @pr: Ptr to acpi_processor containing this CPUs logical Id.
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*
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* Return: 0 for success or negative value for err.
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*/
|
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int acpi_cppc_processor_probe(struct acpi_processor *pr)
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{
|
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struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
|
|
union acpi_object *out_obj, *cpc_obj;
|
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struct cpc_desc *cpc_ptr;
|
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struct cpc_reg *gas_t;
|
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acpi_handle handle = pr->handle;
|
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unsigned int num_ent, i, cpc_rev;
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acpi_status status;
|
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int ret = -EFAULT;
|
|
|
|
/* Parse the ACPI _CPC table for this cpu. */
|
|
status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
|
|
ACPI_TYPE_PACKAGE);
|
|
if (ACPI_FAILURE(status)) {
|
|
ret = -ENODEV;
|
|
goto out_buf_free;
|
|
}
|
|
|
|
out_obj = (union acpi_object *) output.pointer;
|
|
|
|
cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
|
|
if (!cpc_ptr) {
|
|
ret = -ENOMEM;
|
|
goto out_buf_free;
|
|
}
|
|
|
|
/* First entry is NumEntries. */
|
|
cpc_obj = &out_obj->package.elements[0];
|
|
if (cpc_obj->type == ACPI_TYPE_INTEGER) {
|
|
num_ent = cpc_obj->integer.value;
|
|
} else {
|
|
pr_debug("Unexpected entry type(%d) for NumEntries\n",
|
|
cpc_obj->type);
|
|
goto out_free;
|
|
}
|
|
|
|
/* Only support CPPCv2. Bail otherwise. */
|
|
if (num_ent != CPPC_NUM_ENT) {
|
|
pr_debug("Firmware exports %d entries. Expected: %d\n",
|
|
num_ent, CPPC_NUM_ENT);
|
|
goto out_free;
|
|
}
|
|
|
|
/* Second entry should be revision. */
|
|
cpc_obj = &out_obj->package.elements[1];
|
|
if (cpc_obj->type == ACPI_TYPE_INTEGER) {
|
|
cpc_rev = cpc_obj->integer.value;
|
|
} else {
|
|
pr_debug("Unexpected entry type(%d) for Revision\n",
|
|
cpc_obj->type);
|
|
goto out_free;
|
|
}
|
|
|
|
if (cpc_rev != CPPC_REV) {
|
|
pr_debug("Firmware exports revision:%d. Expected:%d\n",
|
|
cpc_rev, CPPC_REV);
|
|
goto out_free;
|
|
}
|
|
|
|
/* Iterate through remaining entries in _CPC */
|
|
for (i = 2; i < num_ent; i++) {
|
|
cpc_obj = &out_obj->package.elements[i];
|
|
|
|
if (cpc_obj->type == ACPI_TYPE_INTEGER) {
|
|
cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
|
|
cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
|
|
} else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
|
|
gas_t = (struct cpc_reg *)
|
|
cpc_obj->buffer.pointer;
|
|
|
|
/*
|
|
* The PCC Subspace index is encoded inside
|
|
* the CPC table entries. The same PCC index
|
|
* will be used for all the PCC entries,
|
|
* so extract it only once.
|
|
*/
|
|
if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
|
|
if (pcc_subspace_idx < 0)
|
|
pcc_subspace_idx = gas_t->access_width;
|
|
else if (pcc_subspace_idx != gas_t->access_width) {
|
|
pr_debug("Mismatched PCC ids.\n");
|
|
goto out_free;
|
|
}
|
|
} else if (gas_t->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) {
|
|
/* Support only PCC and SYS MEM type regs */
|
|
pr_debug("Unsupported register type: %d\n", gas_t->space_id);
|
|
goto out_free;
|
|
}
|
|
|
|
cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
|
|
memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
|
|
} else {
|
|
pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id);
|
|
goto out_free;
|
|
}
|
|
}
|
|
/* Store CPU Logical ID */
|
|
cpc_ptr->cpu_id = pr->id;
|
|
|
|
/* Plug it into this CPUs CPC descriptor. */
|
|
per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
|
|
|
|
/* Parse PSD data for this CPU */
|
|
ret = acpi_get_psd(cpc_ptr, handle);
|
|
if (ret)
|
|
goto out_free;
|
|
|
|
/* Register PCC channel once for all CPUs. */
|
|
if (!pcc_channel_acquired) {
|
|
ret = register_pcc_channel(pcc_subspace_idx);
|
|
if (ret)
|
|
goto out_free;
|
|
}
|
|
|
|
/* Everything looks okay */
|
|
pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
|
|
|
|
kfree(output.pointer);
|
|
return 0;
|
|
|
|
out_free:
|
|
kfree(cpc_ptr);
|
|
|
|
out_buf_free:
|
|
kfree(output.pointer);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
|
|
|
|
/**
|
|
* acpi_cppc_processor_exit - Cleanup CPC structs.
|
|
* @pr: Ptr to acpi_processor containing this CPUs logical Id.
|
|
*
|
|
* Return: Void
|
|
*/
|
|
void acpi_cppc_processor_exit(struct acpi_processor *pr)
|
|
{
|
|
struct cpc_desc *cpc_ptr;
|
|
cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
|
|
kfree(cpc_ptr);
|
|
}
|
|
EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
|
|
|
|
static u64 get_phys_addr(struct cpc_reg *reg)
|
|
{
|
|
/* PCC communication addr space begins at byte offset 0x8. */
|
|
if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM)
|
|
return (u64)comm_base_addr + 0x8 + reg->address;
|
|
else
|
|
return reg->address;
|
|
}
|
|
|
|
static void cpc_read(struct cpc_reg *reg, u64 *val)
|
|
{
|
|
u64 addr = get_phys_addr(reg);
|
|
|
|
acpi_os_read_memory((acpi_physical_address)addr,
|
|
val, reg->bit_width);
|
|
}
|
|
|
|
static void cpc_write(struct cpc_reg *reg, u64 val)
|
|
{
|
|
u64 addr = get_phys_addr(reg);
|
|
|
|
acpi_os_write_memory((acpi_physical_address)addr,
|
|
val, reg->bit_width);
|
|
}
|
|
|
|
/**
|
|
* cppc_get_perf_caps - Get a CPUs performance capabilities.
|
|
* @cpunum: CPU from which to get capabilities info.
|
|
* @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
|
|
*
|
|
* Return: 0 for success with perf_caps populated else -ERRNO.
|
|
*/
|
|
int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
|
|
{
|
|
struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
|
|
struct cpc_register_resource *highest_reg, *lowest_reg, *ref_perf,
|
|
*nom_perf;
|
|
u64 high, low, ref, nom;
|
|
int ret = 0;
|
|
|
|
if (!cpc_desc) {
|
|
pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
|
|
return -ENODEV;
|
|
}
|
|
|
|
highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
|
|
lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
|
|
ref_perf = &cpc_desc->cpc_regs[REFERENCE_PERF];
|
|
nom_perf = &cpc_desc->cpc_regs[NOMINAL_PERF];
|
|
|
|
spin_lock(&pcc_lock);
|
|
|
|
/* Are any of the regs PCC ?*/
|
|
if ((highest_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) ||
|
|
(lowest_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) ||
|
|
(ref_perf->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) ||
|
|
(nom_perf->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM)) {
|
|
/* Ring doorbell once to update PCC subspace */
|
|
if (send_pcc_cmd(CMD_READ)) {
|
|
ret = -EIO;
|
|
goto out_err;
|
|
}
|
|
}
|
|
|
|
cpc_read(&highest_reg->cpc_entry.reg, &high);
|
|
perf_caps->highest_perf = high;
|
|
|
|
cpc_read(&lowest_reg->cpc_entry.reg, &low);
|
|
perf_caps->lowest_perf = low;
|
|
|
|
cpc_read(&ref_perf->cpc_entry.reg, &ref);
|
|
perf_caps->reference_perf = ref;
|
|
|
|
cpc_read(&nom_perf->cpc_entry.reg, &nom);
|
|
perf_caps->nominal_perf = nom;
|
|
|
|
if (!ref)
|
|
perf_caps->reference_perf = perf_caps->nominal_perf;
|
|
|
|
if (!high || !low || !nom)
|
|
ret = -EFAULT;
|
|
|
|
out_err:
|
|
spin_unlock(&pcc_lock);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
|
|
|
|
/**
|
|
* cppc_get_perf_ctrs - Read a CPUs performance feedback counters.
|
|
* @cpunum: CPU from which to read counters.
|
|
* @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
|
|
*
|
|
* Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
|
|
*/
|
|
int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
|
|
{
|
|
struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
|
|
struct cpc_register_resource *delivered_reg, *reference_reg;
|
|
u64 delivered, reference;
|
|
int ret = 0;
|
|
|
|
if (!cpc_desc) {
|
|
pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
|
|
return -ENODEV;
|
|
}
|
|
|
|
delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
|
|
reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
|
|
|
|
spin_lock(&pcc_lock);
|
|
|
|
/* Are any of the regs PCC ?*/
|
|
if ((delivered_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) ||
|
|
(reference_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM)) {
|
|
/* Ring doorbell once to update PCC subspace */
|
|
if (send_pcc_cmd(CMD_READ)) {
|
|
ret = -EIO;
|
|
goto out_err;
|
|
}
|
|
}
|
|
|
|
cpc_read(&delivered_reg->cpc_entry.reg, &delivered);
|
|
cpc_read(&reference_reg->cpc_entry.reg, &reference);
|
|
|
|
if (!delivered || !reference) {
|
|
ret = -EFAULT;
|
|
goto out_err;
|
|
}
|
|
|
|
perf_fb_ctrs->delivered = delivered;
|
|
perf_fb_ctrs->reference = reference;
|
|
|
|
perf_fb_ctrs->delivered -= perf_fb_ctrs->prev_delivered;
|
|
perf_fb_ctrs->reference -= perf_fb_ctrs->prev_reference;
|
|
|
|
perf_fb_ctrs->prev_delivered = delivered;
|
|
perf_fb_ctrs->prev_reference = reference;
|
|
|
|
out_err:
|
|
spin_unlock(&pcc_lock);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
|
|
|
|
/**
|
|
* cppc_set_perf - Set a CPUs performance controls.
|
|
* @cpu: CPU for which to set performance controls.
|
|
* @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
|
|
*
|
|
* Return: 0 for success, -ERRNO otherwise.
|
|
*/
|
|
int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
|
|
{
|
|
struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
|
|
struct cpc_register_resource *desired_reg;
|
|
int ret = 0;
|
|
|
|
if (!cpc_desc) {
|
|
pr_debug("No CPC descriptor for CPU:%d\n", cpu);
|
|
return -ENODEV;
|
|
}
|
|
|
|
desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
|
|
|
|
spin_lock(&pcc_lock);
|
|
|
|
/*
|
|
* Skip writing MIN/MAX until Linux knows how to come up with
|
|
* useful values.
|
|
*/
|
|
cpc_write(&desired_reg->cpc_entry.reg, perf_ctrls->desired_perf);
|
|
|
|
/* Is this a PCC reg ?*/
|
|
if (desired_reg->cpc_entry.reg.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
|
|
/* Ring doorbell so Remote can get our perf request. */
|
|
if (send_pcc_cmd(CMD_WRITE))
|
|
ret = -EIO;
|
|
}
|
|
|
|
spin_unlock(&pcc_lock);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(cppc_set_perf);
|