forked from luck/tmp_suning_uos_patched
16a45bc82e
This patch is part of the series adding support for the USB High Speed Device Port on the AT91CAP9 system on chip. The AT91CAP9 uses the same UDPHS IP as the AVR32 and the AT91SAM9RL. The only differences between the AVR32 and the AT91 version of the device are in the enable/disable and suspend/wakeup sequences: the AT91 version needs to toggle the USB bias and pulldown explicitly. Signed-off-by: Stelian Pop <stelian@popies.net> Acked-by: Andrew Victor <linux@maxim.org.za> Acked-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
359 lines
9.8 KiB
C
359 lines
9.8 KiB
C
/*
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* Driver for the Atmel USBA high speed USB device controller
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*
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* Copyright (C) 2005-2007 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __LINUX_USB_GADGET_USBA_UDC_H__
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#define __LINUX_USB_GADGET_USBA_UDC_H__
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/* USB register offsets */
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#define USBA_CTRL 0x0000
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#define USBA_FNUM 0x0004
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#define USBA_INT_ENB 0x0010
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#define USBA_INT_STA 0x0014
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#define USBA_INT_CLR 0x0018
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#define USBA_EPT_RST 0x001c
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#define USBA_TST 0x00e0
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/* USB endpoint register offsets */
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#define USBA_EPT_CFG 0x0000
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#define USBA_EPT_CTL_ENB 0x0004
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#define USBA_EPT_CTL_DIS 0x0008
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#define USBA_EPT_CTL 0x000c
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#define USBA_EPT_SET_STA 0x0014
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#define USBA_EPT_CLR_STA 0x0018
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#define USBA_EPT_STA 0x001c
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/* USB DMA register offsets */
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#define USBA_DMA_NXT_DSC 0x0000
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#define USBA_DMA_ADDRESS 0x0004
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#define USBA_DMA_CONTROL 0x0008
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#define USBA_DMA_STATUS 0x000c
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/* Bitfields in CTRL */
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#define USBA_DEV_ADDR_OFFSET 0
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#define USBA_DEV_ADDR_SIZE 7
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#define USBA_FADDR_EN (1 << 7)
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#define USBA_EN_USBA (1 << 8)
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#define USBA_DETACH (1 << 9)
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#define USBA_REMOTE_WAKE_UP (1 << 10)
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#define USBA_PULLD_DIS (1 << 11)
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#if defined(CONFIG_AVR32)
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#define USBA_ENABLE_MASK USBA_EN_USBA
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#define USBA_DISABLE_MASK 0
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#elif defined(CONFIG_ARCH_AT91)
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#define USBA_ENABLE_MASK (USBA_EN_USBA | USBA_PULLD_DIS)
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#define USBA_DISABLE_MASK USBA_DETACH
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#endif /* CONFIG_ARCH_AT91 */
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/* Bitfields in FNUM */
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#define USBA_MICRO_FRAME_NUM_OFFSET 0
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#define USBA_MICRO_FRAME_NUM_SIZE 3
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#define USBA_FRAME_NUMBER_OFFSET 3
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#define USBA_FRAME_NUMBER_SIZE 11
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#define USBA_FRAME_NUM_ERROR (1 << 31)
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/* Bitfields in INT_ENB/INT_STA/INT_CLR */
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#define USBA_HIGH_SPEED (1 << 0)
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#define USBA_DET_SUSPEND (1 << 1)
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#define USBA_MICRO_SOF (1 << 2)
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#define USBA_SOF (1 << 3)
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#define USBA_END_OF_RESET (1 << 4)
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#define USBA_WAKE_UP (1 << 5)
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#define USBA_END_OF_RESUME (1 << 6)
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#define USBA_UPSTREAM_RESUME (1 << 7)
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#define USBA_EPT_INT_OFFSET 8
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#define USBA_EPT_INT_SIZE 16
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#define USBA_DMA_INT_OFFSET 24
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#define USBA_DMA_INT_SIZE 8
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/* Bitfields in EPT_RST */
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#define USBA_RST_OFFSET 0
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#define USBA_RST_SIZE 16
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/* Bitfields in USBA_TST */
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#define USBA_SPEED_CFG_OFFSET 0
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#define USBA_SPEED_CFG_SIZE 2
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#define USBA_TST_J_MODE (1 << 2)
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#define USBA_TST_K_MODE (1 << 3)
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#define USBA_TST_PKT_MODE (1 << 4)
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#define USBA_OPMODE2 (1 << 5)
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/* Bitfields in EPT_CFG */
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#define USBA_EPT_SIZE_OFFSET 0
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#define USBA_EPT_SIZE_SIZE 3
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#define USBA_EPT_DIR_IN (1 << 3)
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#define USBA_EPT_TYPE_OFFSET 4
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#define USBA_EPT_TYPE_SIZE 2
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#define USBA_BK_NUMBER_OFFSET 6
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#define USBA_BK_NUMBER_SIZE 2
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#define USBA_NB_TRANS_OFFSET 8
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#define USBA_NB_TRANS_SIZE 2
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#define USBA_EPT_MAPPED (1 << 31)
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/* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */
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#define USBA_EPT_ENABLE (1 << 0)
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#define USBA_AUTO_VALID (1 << 1)
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#define USBA_INTDIS_DMA (1 << 3)
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#define USBA_NYET_DIS (1 << 4)
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#define USBA_DATAX_RX (1 << 6)
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#define USBA_MDATA_RX (1 << 7)
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/* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */
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#define USBA_BUSY_BANK_IE (1 << 18)
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/* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */
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#define USBA_FORCE_STALL (1 << 5)
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#define USBA_TOGGLE_CLR (1 << 6)
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#define USBA_TOGGLE_SEQ_OFFSET 6
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#define USBA_TOGGLE_SEQ_SIZE 2
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#define USBA_ERR_OVFLW (1 << 8)
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#define USBA_RX_BK_RDY (1 << 9)
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#define USBA_KILL_BANK (1 << 9)
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#define USBA_TX_COMPLETE (1 << 10)
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#define USBA_TX_PK_RDY (1 << 11)
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#define USBA_ISO_ERR_TRANS (1 << 11)
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#define USBA_RX_SETUP (1 << 12)
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#define USBA_ISO_ERR_FLOW (1 << 12)
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#define USBA_STALL_SENT (1 << 13)
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#define USBA_ISO_ERR_CRC (1 << 13)
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#define USBA_ISO_ERR_NBTRANS (1 << 13)
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#define USBA_NAK_IN (1 << 14)
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#define USBA_ISO_ERR_FLUSH (1 << 14)
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#define USBA_NAK_OUT (1 << 15)
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#define USBA_CURRENT_BANK_OFFSET 16
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#define USBA_CURRENT_BANK_SIZE 2
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#define USBA_BUSY_BANKS_OFFSET 18
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#define USBA_BUSY_BANKS_SIZE 2
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#define USBA_BYTE_COUNT_OFFSET 20
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#define USBA_BYTE_COUNT_SIZE 11
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#define USBA_SHORT_PACKET (1 << 31)
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/* Bitfields in DMA_CONTROL */
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#define USBA_DMA_CH_EN (1 << 0)
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#define USBA_DMA_LINK (1 << 1)
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#define USBA_DMA_END_TR_EN (1 << 2)
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#define USBA_DMA_END_BUF_EN (1 << 3)
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#define USBA_DMA_END_TR_IE (1 << 4)
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#define USBA_DMA_END_BUF_IE (1 << 5)
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#define USBA_DMA_DESC_LOAD_IE (1 << 6)
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#define USBA_DMA_BURST_LOCK (1 << 7)
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#define USBA_DMA_BUF_LEN_OFFSET 16
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#define USBA_DMA_BUF_LEN_SIZE 16
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/* Bitfields in DMA_STATUS */
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#define USBA_DMA_CH_ACTIVE (1 << 1)
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#define USBA_DMA_END_TR_ST (1 << 4)
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#define USBA_DMA_END_BUF_ST (1 << 5)
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#define USBA_DMA_DESC_LOAD_ST (1 << 6)
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/* Constants for SPEED_CFG */
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#define USBA_SPEED_CFG_NORMAL 0
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#define USBA_SPEED_CFG_FORCE_HIGH 2
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#define USBA_SPEED_CFG_FORCE_FULL 3
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/* Constants for EPT_SIZE */
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#define USBA_EPT_SIZE_8 0
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#define USBA_EPT_SIZE_16 1
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#define USBA_EPT_SIZE_32 2
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#define USBA_EPT_SIZE_64 3
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#define USBA_EPT_SIZE_128 4
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#define USBA_EPT_SIZE_256 5
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#define USBA_EPT_SIZE_512 6
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#define USBA_EPT_SIZE_1024 7
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/* Constants for EPT_TYPE */
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#define USBA_EPT_TYPE_CONTROL 0
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#define USBA_EPT_TYPE_ISO 1
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#define USBA_EPT_TYPE_BULK 2
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#define USBA_EPT_TYPE_INT 3
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/* Constants for BK_NUMBER */
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#define USBA_BK_NUMBER_ZERO 0
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#define USBA_BK_NUMBER_ONE 1
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#define USBA_BK_NUMBER_DOUBLE 2
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#define USBA_BK_NUMBER_TRIPLE 3
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/* Bit manipulation macros */
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#define USBA_BF(name, value) \
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(((value) & ((1 << USBA_##name##_SIZE) - 1)) \
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<< USBA_##name##_OFFSET)
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#define USBA_BFEXT(name, value) \
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(((value) >> USBA_##name##_OFFSET) \
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& ((1 << USBA_##name##_SIZE) - 1))
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#define USBA_BFINS(name, value, old) \
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(((old) & ~(((1 << USBA_##name##_SIZE) - 1) \
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<< USBA_##name##_OFFSET)) \
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| USBA_BF(name, value))
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/* Register access macros */
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#define usba_readl(udc, reg) \
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__raw_readl((udc)->regs + USBA_##reg)
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#define usba_writel(udc, reg, value) \
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__raw_writel((value), (udc)->regs + USBA_##reg)
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#define usba_ep_readl(ep, reg) \
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__raw_readl((ep)->ep_regs + USBA_EPT_##reg)
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#define usba_ep_writel(ep, reg, value) \
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__raw_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
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#define usba_dma_readl(ep, reg) \
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__raw_readl((ep)->dma_regs + USBA_DMA_##reg)
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#define usba_dma_writel(ep, reg, value) \
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__raw_writel((value), (ep)->dma_regs + USBA_DMA_##reg)
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/* Calculate base address for a given endpoint or DMA controller */
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#define USBA_EPT_BASE(x) (0x100 + (x) * 0x20)
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#define USBA_DMA_BASE(x) (0x300 + (x) * 0x10)
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#define USBA_FIFO_BASE(x) ((x) << 16)
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/* Synth parameters */
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#define USBA_NR_ENDPOINTS 7
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#define EP0_FIFO_SIZE 64
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#define EP0_EPT_SIZE USBA_EPT_SIZE_64
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#define EP0_NR_BANKS 1
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/*
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* REVISIT: Try to eliminate this value. Can we rely on req->mapped to
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* provide this information?
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*/
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#define DMA_ADDR_INVALID (~(dma_addr_t)0)
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#define FIFO_IOMEM_ID 0
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#define CTRL_IOMEM_ID 1
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#define DBG_ERR 0x0001 /* report all error returns */
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#define DBG_HW 0x0002 /* debug hardware initialization */
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#define DBG_GADGET 0x0004 /* calls to/from gadget driver */
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#define DBG_INT 0x0008 /* interrupts */
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#define DBG_BUS 0x0010 /* report changes in bus state */
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#define DBG_QUEUE 0x0020 /* debug request queue processing */
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#define DBG_FIFO 0x0040 /* debug FIFO contents */
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#define DBG_DMA 0x0080 /* debug DMA handling */
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#define DBG_REQ 0x0100 /* print out queued request length */
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#define DBG_ALL 0xffff
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#define DBG_NONE 0x0000
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#define DEBUG_LEVEL (DBG_ERR)
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#define DBG(level, fmt, ...) \
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do { \
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if ((level) & DEBUG_LEVEL) \
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pr_debug("udc: " fmt, ## __VA_ARGS__); \
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} while (0)
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enum usba_ctrl_state {
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WAIT_FOR_SETUP,
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DATA_STAGE_IN,
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DATA_STAGE_OUT,
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STATUS_STAGE_IN,
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STATUS_STAGE_OUT,
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STATUS_STAGE_ADDR,
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STATUS_STAGE_TEST,
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};
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/*
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EP_STATE_IDLE,
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EP_STATE_SETUP,
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EP_STATE_IN_DATA,
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EP_STATE_OUT_DATA,
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EP_STATE_SET_ADDR_STATUS,
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EP_STATE_RX_STATUS,
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EP_STATE_TX_STATUS,
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EP_STATE_HALT,
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*/
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struct usba_dma_desc {
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dma_addr_t next;
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dma_addr_t addr;
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u32 ctrl;
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};
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struct usba_ep {
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int state;
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void __iomem *ep_regs;
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void __iomem *dma_regs;
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void __iomem *fifo;
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struct usb_ep ep;
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struct usba_udc *udc;
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struct list_head queue;
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const struct usb_endpoint_descriptor *desc;
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u16 fifo_size;
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u8 nr_banks;
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u8 index;
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unsigned int can_dma:1;
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unsigned int can_isoc:1;
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unsigned int is_isoc:1;
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unsigned int is_in:1;
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#ifdef CONFIG_USB_GADGET_DEBUG_FS
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u32 last_dma_status;
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struct dentry *debugfs_dir;
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struct dentry *debugfs_queue;
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struct dentry *debugfs_dma_status;
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struct dentry *debugfs_state;
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#endif
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};
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struct usba_request {
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struct usb_request req;
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struct list_head queue;
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u32 ctrl;
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unsigned int submitted:1;
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unsigned int last_transaction:1;
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unsigned int using_dma:1;
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unsigned int mapped:1;
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};
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struct usba_udc {
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/* Protect hw registers from concurrent modifications */
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spinlock_t lock;
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void __iomem *regs;
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void __iomem *fifo;
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struct usb_gadget gadget;
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struct usb_gadget_driver *driver;
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struct platform_device *pdev;
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int irq;
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int vbus_pin;
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struct clk *pclk;
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struct clk *hclk;
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u16 devstatus;
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u16 test_mode;
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int vbus_prev;
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#ifdef CONFIG_USB_GADGET_DEBUG_FS
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struct dentry *debugfs_root;
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struct dentry *debugfs_regs;
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#endif
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};
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static inline struct usba_ep *to_usba_ep(struct usb_ep *ep)
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{
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return container_of(ep, struct usba_ep, ep);
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}
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static inline struct usba_request *to_usba_req(struct usb_request *req)
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{
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return container_of(req, struct usba_request, req);
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}
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static inline struct usba_udc *to_usba_udc(struct usb_gadget *gadget)
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{
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return container_of(gadget, struct usba_udc, gadget);
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}
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#define ep_is_control(ep) ((ep)->index == 0)
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#define ep_is_idle(ep) ((ep)->state == EP_STATE_IDLE)
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#endif /* __LINUX_USB_GADGET_USBA_UDC_H */
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