forked from luck/tmp_suning_uos_patched
bb89e7141a
typo: "a7mode" chooses whether to use bits {8, 7, 9} or {8, 7, 6} in the algorithm to spread access between memory resources. But the non-a7mode path was incorrectly using GET_BITFIELD(addr, 7, 9) and so picking bits {9, 8, 7} thinko: BIT(1) of the dram_rule registers chooses whether to just use the {8, 7, 6} (or {8, 7, 9}) bits mentioned above as they are, or to XOR them with bits {18, 17, 16} but the code inverted the test. We need the additional XOR when dram_rule{1} == 0. Signed-off-by: Tony Luck <tony.luck@intel.com> Acked-by: Aristeu Rozanski <aris@redhat.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> |
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.. | ||
altera_edac.c | ||
amd64_edac_dbg.c | ||
amd64_edac_inj.c | ||
amd64_edac.c | ||
amd64_edac.h | ||
amd76x_edac.c | ||
amd8111_edac.c | ||
amd8111_edac.h | ||
amd8131_edac.c | ||
amd8131_edac.h | ||
cell_edac.c | ||
cpc925_edac.c | ||
e7xxx_edac.c | ||
e752x_edac.c | ||
edac_core.h | ||
edac_device_sysfs.c | ||
edac_device.c | ||
edac_mc_sysfs.c | ||
edac_mc.c | ||
edac_module.c | ||
edac_module.h | ||
edac_pci_sysfs.c | ||
edac_pci.c | ||
edac_stub.c | ||
ghes_edac.c | ||
highbank_l2_edac.c | ||
highbank_mc_edac.c | ||
i7core_edac.c | ||
i3000_edac.c | ||
i3200_edac.c | ||
i5000_edac.c | ||
i5100_edac.c | ||
i5400_edac.c | ||
i7300_edac.c | ||
i82443bxgx_edac.c | ||
i82860_edac.c | ||
i82875p_edac.c | ||
i82975x_edac.c | ||
ie31200_edac.c | ||
Kconfig | ||
Makefile | ||
mce_amd_inj.c | ||
mce_amd.c | ||
mce_amd.h | ||
mpc85xx_edac.c | ||
mpc85xx_edac.h | ||
mv64x60_edac.c | ||
mv64x60_edac.h | ||
octeon_edac-l2c.c | ||
octeon_edac-lmc.c | ||
octeon_edac-pc.c | ||
octeon_edac-pci.c | ||
pasemi_edac.c | ||
ppc4xx_edac.c | ||
ppc4xx_edac.h | ||
r82600_edac.c | ||
sb_edac.c | ||
synopsys_edac.c | ||
tile_edac.c | ||
x38_edac.c |