Marc Zyngier a5325089bd arm64: Handle erratum 1418040 as a superset of erratum 1188873 ... We already mitigate erratum 1188873 affecting Cortex-A76 and Neoverse-N1 r0p0 to r2p0. It turns out that revisions r0p0 to r3p1 of the same cores are affected by erratum 1418040, which has the same workaround as 1188873. Let's expand the range of affected revisions to match 1418040, and repaint all occurences of 1188873 to 1418040. Whilst we're there, do a bit of reformating in silicon-errata.txt and drop a now unnecessary dependency on ARM_ARCH_TIMER_OOL_WORKAROUND. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>		2019-05-23 15:40:30 +01:00
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acpi_object_usage.txt
arm-acpi.txt
booting.txt	irqchip/gic-v3: Detect if GIC can support pseudo-NMIs	2019-02-06 10:05:21 +00:00
cpu-feature-registers.txt	arm64: Expose SVE2 features for userspace	2019-04-23 18:02:00 +01:00
elf_hwcaps.txt	arm64: Expose SVE2 features for userspace	2019-04-23 18:02:00 +01:00
hugetlbpage.txt	Documentation/arm64: HugeTLB page implementation	2018-10-10 18:08:36 +01:00
legacy_instructions.txt
memory.txt
perf.txt	arm64: docs: Document perf event attributes	2019-04-24 15:46:26 +01:00
pointer-authentication.txt	KVM: arm64: Add userspace flag to enable pointer authentication	2019-04-24 15:30:40 +01:00
silicon-errata.txt	arm64: Handle erratum 1418040 as a superset of erratum 1188873	2019-05-23 15:40:30 +01:00
sve.txt	arm64: Expose SVE2 features for userspace	2019-04-23 18:02:00 +01:00
tagged-pointers.txt