AcoSail/kernel_optimize_test
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kernel_optimize_test/arch/arm64/kvm
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Marc Zyngier f142e5eeb7 arm64: KVM: add missing dsb before invalidating Stage-2 TLBs 
When performing a Stage-2 TLB invalidation, it is necessary to
make sure the write to the page tables is observable by all CPUs.

For this purpose, add dsb instructions to __kvm_tlb_flush_vmid_ipa
and __kvm_flush_vm_context before doing the TLB invalidation itself.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-08-09 13:19:28 +01:00
..
emulate.c arm64: KVM: 32bit conditional execution emulation 2013-06-12 16:42:15 +01:00
guest.c arm64: KVM: enable initialization of a 32bit vcpu 2013-06-12 16:42:18 +01:00
handle_exit.c arm64: KVM: 32bit handling of coprocessor traps 2013-06-12 16:42:16 +01:00
hyp-init.S arm64: KVM: hypervisor initialization code 2013-06-07 14:03:40 +01:00
hyp.S arm64: KVM: add missing dsb before invalidating Stage-2 TLBs 2013-08-09 13:19:28 +01:00
inject_fault.c arm64: KVM: 32bit guest fault injection 2013-06-12 16:42:18 +01:00
Kconfig arm64: KVM: Kconfig integration 2013-07-04 14:40:26 +02:00
Makefile arm64: KVM: 32bit conditional execution emulation 2013-06-12 16:42:15 +01:00
regmap.c arm64: KVM: 32bit GP register access 2013-06-12 16:42:14 +01:00
reset.c arm64: KVM: enable initialization of a 32bit vcpu 2013-06-12 16:42:18 +01:00
sys_regs_generic_v8.c arm64: KVM: CPU specific 32bit coprocessor access 2013-06-12 16:42:16 +01:00
sys_regs.c arm64: KVM: perform save/restore of PAR_EL1 2013-08-09 13:19:28 +01:00
sys_regs.h