forked from luck/tmp_suning_uos_patched
be40eecf8d
Add functions which configure the control module register CTRL_CORE_DSS_PLL_CONTROL found in DRA7xx SoCs. This register configures whether the PLL registers are accessed internally by DSS, or externally using OCP2SCP interface. They also configure muxes which route the PLL output to a particular LCD overlay manager within DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> |
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.. | ||
backlight | ||
console | ||
fbdev | ||
logo | ||
display_timing.c | ||
hdmi.c | ||
Kconfig | ||
Makefile | ||
of_display_timing.c | ||
of_videomode.c | ||
vgastate.c | ||
videomode.c |