forked from luck/tmp_suning_uos_patched
2e554390ab
BG2CD SoC uses r3p0 Cortex-A9 MPCore single-CPU cluster. Autoselect pertinent errata, the SCU and the global timer, and allow use of the local timer on uniprocessor kernels. PL310 L2 cache controller has revision r3p2; no errata to select. Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
42 lines
866 B
Plaintext
42 lines
866 B
Plaintext
menuconfig ARCH_BERLIN
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bool "Marvell Berlin SoCs"
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depends on ARCH_MULTI_V7
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select ARCH_HAS_RESET_CONTROLLER
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select ARM_GIC
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select DW_APB_ICTL
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select DW_APB_TIMER_OF
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select GENERIC_IRQ_CHIP
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select GPIOLIB
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select MFD_SYSCON
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select PINCTRL
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if ARCH_BERLIN
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config MACH_BERLIN_BG2
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bool "Marvell Armada 1500 (BG2)"
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select CACHE_L2X0
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select CPU_PJ4B
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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select HAVE_SMP
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select PINCTRL_BERLIN_BG2
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config MACH_BERLIN_BG2CD
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bool "Marvell Armada 1500-mini (BG2CD)"
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select ARM_ERRATA_754322
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select ARM_ERRATA_775420
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select ARM_GLOBAL_TIMER
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select CACHE_L2X0
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select HAVE_ARM_SCU
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select HAVE_ARM_TWD
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select PINCTRL_BERLIN_BG2CD
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config MACH_BERLIN_BG2Q
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bool "Marvell Armada 1500 Pro (BG2-Q)"
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select CACHE_L2X0
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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select PINCTRL_BERLIN_BG2Q
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endif
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