forked from luck/tmp_suning_uos_patched
3f9fb2a08f
The mach/cns3xxx.h and mach/pm.h header files are used only in the platform code itself, so there is no need to make them globally visible. This gets us closer to multiplatform configuration for cns3xxx. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
112 lines
2.6 KiB
C
112 lines
2.6 KiB
C
/*
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* CNS3xxx common devices
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*
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* Copyright 2008 Cavium Networks
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* Scott Shu
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* Copyright 2010 MontaVista Software, LLC.
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* Anton Vorontsov <avorontsov@mvista.com>
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/compiler.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include "cns3xxx.h"
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#include "pm.h"
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#include "core.h"
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#include "devices.h"
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/*
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* AHCI
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*/
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static struct resource cns3xxx_ahci_resource[] = {
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[0] = {
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.start = CNS3XXX_SATA2_BASE,
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.end = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_CNS3XXX_SATA,
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.end = IRQ_CNS3XXX_SATA,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
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static struct platform_device cns3xxx_ahci_pdev = {
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.name = "ahci",
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.id = 0,
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.resource = cns3xxx_ahci_resource,
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.num_resources = ARRAY_SIZE(cns3xxx_ahci_resource),
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.dev = {
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.dma_mask = &cns3xxx_ahci_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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void __init cns3xxx_ahci_init(void)
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{
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u32 tmp;
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tmp = __raw_readl(MISC_SATA_POWER_MODE);
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tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
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tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
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__raw_writel(tmp, MISC_SATA_POWER_MODE);
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/* Enable SATA PHY */
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cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
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cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
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/* Enable SATA Clock */
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cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
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/* De-Asscer SATA Reset */
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cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
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platform_device_register(&cns3xxx_ahci_pdev);
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}
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/*
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* SDHCI
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*/
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static struct resource cns3xxx_sdhci_resources[] = {
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[0] = {
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.start = CNS3XXX_SDIO_BASE,
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.end = CNS3XXX_SDIO_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_CNS3XXX_SDIO,
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.end = IRQ_CNS3XXX_SDIO,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device cns3xxx_sdhci_pdev = {
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.name = "sdhci-cns3xxx",
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.id = 0,
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.num_resources = ARRAY_SIZE(cns3xxx_sdhci_resources),
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.resource = cns3xxx_sdhci_resources,
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};
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void __init cns3xxx_sdhci_init(void)
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{
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u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
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u32 gpioa_pins = __raw_readl(gpioa);
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/* MMC/SD pins share with GPIOA */
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gpioa_pins |= 0x1fff0004;
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__raw_writel(gpioa_pins, gpioa);
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cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
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cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
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platform_device_register(&cns3xxx_sdhci_pdev);
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}
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