kernel_optimize_test/arch/mips/bmips/irq.c
Simon Arlott c7c42ec2ba irqchips/bmips: Add bcm6345-l1 interrupt controller
Add the BCM6345 interrupt controller based on the SMP-capable BCM7038
and the BCM3380 but with packed interrupt registers.

Add the BCM6345 interrupt controller to a list with the existing BCM7038
so that interrupts on CPU1 are not ignored.

Update the maintainers file list for BMIPS to include this driver.

Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: linux-mips@linux-mips.org
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Rob Herring <robh@kernel.org>
Link: http://lkml.kernel.org/r/5651D176.6030908@simon.arlott.org.uk
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-02-08 15:03:42 +01:00

45 lines
994 B
C

/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2014 Broadcom Corporation
* Author: Kevin Cernekee <cernekee@gmail.com>
*/
#include <linux/of.h>
#include <linux/irqchip.h>
#include <asm/bmips.h>
#include <asm/irq.h>
#include <asm/irq_cpu.h>
#include <asm/time.h>
static const struct of_device_id smp_intc_dt_match[] = {
{ .compatible = "brcm,bcm7038-l1-intc" },
{ .compatible = "brcm,bcm6345-l1-intc" },
{}
};
unsigned int get_c0_compare_int(void)
{
return CP0_LEGACY_COMPARE_IRQ;
}
void __init arch_init_irq(void)
{
struct device_node *dn;
/* Only these controllers support SMP IRQ affinity */
dn = of_find_matching_node(NULL, smp_intc_dt_match);
if (dn)
of_node_put(dn);
else
bmips_tp1_irqs = 0;
irqchip_init();
}
IRQCHIP_DECLARE(mips_cpu_intc, "mti,cpu-interrupt-controller",
mips_cpu_irq_of_init);