forked from luck/tmp_suning_uos_patched
90303b1023
Patch from Catalin Marinas If the low interrupt latency mode is enabled for the CPU (from ARMv6 onwards), the ldm/stm instructions are no longer atomic. An ldm instruction restoring the sp and pc registers can be interrupted immediately after sp was updated but before the pc. If this happens, the CPU restores the base register to the value before the ldm instruction but if the base register is not sp, the interrupt routine will corrupt the stack and the restarted ldm instruction will load garbage. Note that future ARM cores might always run in the low interrupt latency mode. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
55 lines
1.1 KiB
ArmAsm
55 lines
1.1 KiB
ArmAsm
/*
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* linux/arch/arm/lib/csumpartialcopy.S
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*
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* Copyright (C) 1995-1998 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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.text
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/* Function: __u32 csum_partial_copy_nocheck(const char *src, char *dst, int len, __u32 sum)
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* Params : r0 = src, r1 = dst, r2 = len, r3 = checksum
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* Returns : r0 = new checksum
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*/
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.macro save_regs
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mov ip, sp
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stmfd sp!, {r1, r4 - r8, fp, ip, lr, pc}
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sub fp, ip, #4
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.endm
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.macro load_regs
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ldmfd sp, {r1, r4 - r8, fp, sp, pc}
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.endm
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.macro load1b, reg1
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ldrb \reg1, [r0], #1
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.endm
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.macro load2b, reg1, reg2
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ldrb \reg1, [r0], #1
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ldrb \reg2, [r0], #1
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.endm
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.macro load1l, reg1
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ldr \reg1, [r0], #4
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.endm
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.macro load2l, reg1, reg2
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ldr \reg1, [r0], #4
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ldr \reg2, [r0], #4
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.endm
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.macro load4l, reg1, reg2, reg3, reg4
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ldmia r0!, {\reg1, \reg2, \reg3, \reg4}
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.endm
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#define FN_ENTRY ENTRY(csum_partial_copy_nocheck)
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#include "csumpartialcopygeneric.S"
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