forked from luck/tmp_suning_uos_patched
c214455f32
On secondary CPUs, the Timer Control Register is not reset to a sane value before the timer is registered, and the TRM doesn't seem to indicate any reset value either. In some cases, the kernel will take an interrupt too early, depending on what junk was present in the registers at reset time. The fix is to set the Timer Control Register to 0 before registering the clock_event_device and enabling the interrupt. Problem seen on VE (Cortex A5) and Tegra. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
271 lines
6.0 KiB
C
271 lines
6.0 KiB
C
/*
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* linux/arch/arm/kernel/smp_twd.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/smp.h>
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#include <linux/jiffies.h>
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#include <linux/clockchips.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/smp_twd.h>
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#include <asm/localtimer.h>
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#include <asm/hardware/gic.h>
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/* set up by the platform code */
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void __iomem *twd_base;
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static struct clk *twd_clk;
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static unsigned long twd_timer_rate;
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static struct clock_event_device __percpu **twd_evt;
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static void twd_set_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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unsigned long ctrl;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* timer load already set up */
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ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
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| TWD_TIMER_CONTROL_PERIODIC;
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__raw_writel(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* period set, and timer enabled in 'next_event' hook */
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ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT;
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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ctrl = 0;
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}
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__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
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}
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static int twd_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
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ctrl |= TWD_TIMER_CONTROL_ENABLE;
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__raw_writel(evt, twd_base + TWD_TIMER_COUNTER);
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__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
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return 0;
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}
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/*
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* local_timer_ack: checks for a local timer interrupt.
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*
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* If a local timer interrupt has occurred, acknowledge and return 1.
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* Otherwise, return 0.
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*/
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int twd_timer_ack(void)
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{
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if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
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__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
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return 1;
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}
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return 0;
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}
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void twd_timer_stop(struct clock_event_device *clk)
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{
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twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
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disable_percpu_irq(clk->irq);
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}
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#ifdef CONFIG_CPU_FREQ
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/*
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* Updates clockevent frequency when the cpu frequency changes.
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* Called on the cpu that is changing frequency with interrupts disabled.
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*/
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static void twd_update_frequency(void *data)
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{
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twd_timer_rate = clk_get_rate(twd_clk);
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clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate);
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}
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static int twd_cpufreq_transition(struct notifier_block *nb,
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unsigned long state, void *data)
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{
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struct cpufreq_freqs *freqs = data;
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/*
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* The twd clock events must be reprogrammed to account for the new
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* frequency. The timer is local to a cpu, so cross-call to the
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* changing cpu.
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*/
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if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE)
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smp_call_function_single(freqs->cpu, twd_update_frequency,
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NULL, 1);
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return NOTIFY_OK;
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}
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static struct notifier_block twd_cpufreq_nb = {
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.notifier_call = twd_cpufreq_transition,
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};
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static int twd_cpufreq_init(void)
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{
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if (!IS_ERR(twd_clk))
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return cpufreq_register_notifier(&twd_cpufreq_nb,
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CPUFREQ_TRANSITION_NOTIFIER);
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return 0;
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}
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core_initcall(twd_cpufreq_init);
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#endif
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static void __cpuinit twd_calibrate_rate(void)
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{
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unsigned long count;
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u64 waitjiffies;
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/*
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* If this is the first time round, we need to work out how fast
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* the timer ticks
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*/
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if (twd_timer_rate == 0) {
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printk(KERN_INFO "Calibrating local timer... ");
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/* Wait for a tick to start */
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waitjiffies = get_jiffies_64() + 1;
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while (get_jiffies_64() < waitjiffies)
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udelay(10);
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/* OK, now the tick has started, let's get the timer going */
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waitjiffies += 5;
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/* enable, no interrupt or reload */
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__raw_writel(0x1, twd_base + TWD_TIMER_CONTROL);
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/* maximum value */
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__raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
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while (get_jiffies_64() < waitjiffies)
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udelay(10);
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count = __raw_readl(twd_base + TWD_TIMER_COUNTER);
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twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
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printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000,
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(twd_timer_rate / 10000) % 100);
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}
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}
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static irqreturn_t twd_handler(int irq, void *dev_id)
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{
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struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
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if (twd_timer_ack()) {
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static struct clk *twd_get_clock(void)
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{
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struct clk *clk;
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int err;
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clk = clk_get_sys("smp_twd", NULL);
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if (IS_ERR(clk)) {
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pr_err("smp_twd: clock not found: %d\n", (int)PTR_ERR(clk));
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return clk;
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}
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err = clk_prepare(clk);
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if (err) {
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pr_err("smp_twd: clock failed to prepare: %d\n", err);
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clk_put(clk);
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return ERR_PTR(err);
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}
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err = clk_enable(clk);
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if (err) {
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pr_err("smp_twd: clock failed to enable: %d\n", err);
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clk_unprepare(clk);
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clk_put(clk);
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return ERR_PTR(err);
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}
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return clk;
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}
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/*
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* Setup the local clock events for a CPU.
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*/
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void __cpuinit twd_timer_setup(struct clock_event_device *clk)
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{
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struct clock_event_device **this_cpu_clk;
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if (!twd_evt) {
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int err;
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twd_evt = alloc_percpu(struct clock_event_device *);
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if (!twd_evt) {
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pr_err("twd: can't allocate memory\n");
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return;
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}
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err = request_percpu_irq(clk->irq, twd_handler,
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"twd", twd_evt);
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if (err) {
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pr_err("twd: can't register interrupt %d (%d)\n",
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clk->irq, err);
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return;
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}
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}
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if (!twd_clk)
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twd_clk = twd_get_clock();
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if (!IS_ERR_OR_NULL(twd_clk))
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twd_timer_rate = clk_get_rate(twd_clk);
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else
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twd_calibrate_rate();
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__raw_writel(0, twd_base + TWD_TIMER_CONTROL);
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clk->name = "local_timer";
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clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_C3STOP;
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clk->rating = 350;
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clk->set_mode = twd_set_mode;
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clk->set_next_event = twd_set_next_event;
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this_cpu_clk = __this_cpu_ptr(twd_evt);
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*this_cpu_clk = clk;
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clockevents_config_and_register(clk, twd_timer_rate,
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0xf, 0xffffffff);
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enable_percpu_irq(clk->irq, 0);
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}
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