forked from luck/tmp_suning_uos_patched
c4236d2e79
While coming out of MPU OSWR/OFF states, L2 controller is reseted. The reset behavior is implementation specific as per ARMv7 TRM and hence $L2 needs to be invalidated before it's use. Since the AUXCTRL register is also reconfigured, disable L2 cache before invalidating it and re-enables it afterwards. This is as per Cortex-A8 ARM documentation. Currently this is identified as being needed on OMAP3630 as the disable/enable is done from "public side" while, on OMAP3430, this is done in the "secure side". Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Jean Pihet <j-pihet@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630] Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
100 lines
3.1 KiB
C
100 lines
3.1 KiB
C
/*
|
|
* OMAP2/3 Power Management Routines
|
|
*
|
|
* Copyright (C) 2008 Nokia Corporation
|
|
* Jouni Hogander
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
#ifndef __ARCH_ARM_MACH_OMAP2_PM_H
|
|
#define __ARCH_ARM_MACH_OMAP2_PM_H
|
|
|
|
#include <plat/powerdomain.h>
|
|
|
|
extern void *omap3_secure_ram_storage;
|
|
extern void omap3_pm_off_mode_enable(int);
|
|
extern void omap_sram_idle(void);
|
|
extern int omap3_can_sleep(void);
|
|
extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
|
|
extern int omap3_idle_init(void);
|
|
|
|
struct cpuidle_params {
|
|
u8 valid;
|
|
u32 sleep_latency;
|
|
u32 wake_latency;
|
|
u32 threshold;
|
|
};
|
|
|
|
#if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE)
|
|
extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params);
|
|
#else
|
|
static
|
|
inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
|
|
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
|
|
|
|
extern u32 wakeup_timer_seconds;
|
|
extern u32 wakeup_timer_milliseconds;
|
|
extern struct omap_dm_timer *gptimer_wakeup;
|
|
|
|
#ifdef CONFIG_PM_DEBUG
|
|
extern void omap2_pm_dump(int mode, int resume, unsigned int us);
|
|
extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds);
|
|
extern int omap2_pm_debug;
|
|
extern u32 enable_off_mode;
|
|
extern u32 sleep_while_idle;
|
|
#else
|
|
#define omap2_pm_dump(mode, resume, us) do {} while (0);
|
|
#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0);
|
|
#define omap2_pm_debug 0
|
|
#define enable_off_mode 0
|
|
#define sleep_while_idle 0
|
|
#endif
|
|
|
|
#if defined(CONFIG_CPU_IDLE)
|
|
extern void omap3_cpuidle_update_states(void);
|
|
#endif
|
|
|
|
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
|
|
extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
|
|
extern int pm_dbg_regset_save(int reg_set);
|
|
extern int pm_dbg_regset_init(int reg_set);
|
|
#else
|
|
#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
|
|
#define pm_dbg_regset_save(reg_set) do {} while (0);
|
|
#define pm_dbg_regset_init(reg_set) do {} while (0);
|
|
#endif /* CONFIG_PM_DEBUG */
|
|
|
|
extern void omap24xx_idle_loop_suspend(void);
|
|
|
|
extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
|
|
void __iomem *sdrc_power);
|
|
extern void omap34xx_cpu_suspend(u32 *addr, int save_state);
|
|
extern void save_secure_ram_context(u32 *addr);
|
|
extern void omap3_save_scratchpad_contents(void);
|
|
|
|
extern unsigned int omap24xx_idle_loop_suspend_sz;
|
|
extern unsigned int omap34xx_suspend_sz;
|
|
extern unsigned int save_secure_ram_context_sz;
|
|
extern unsigned int omap24xx_cpu_suspend_sz;
|
|
extern unsigned int omap34xx_cpu_suspend_sz;
|
|
|
|
#define PM_RTA_ERRATUM_i608 (1 << 0)
|
|
|
|
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
|
|
extern u16 pm34xx_errata;
|
|
#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
|
|
extern void enable_omap3630_toggle_l2_on_restore(void);
|
|
#else
|
|
#define IS_PM34XX_ERRATUM(id) 0
|
|
static inline void enable_omap3630_toggle_l2_on_restore(void) { }
|
|
#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
|
|
|
|
#endif
|