forked from luck/tmp_suning_uos_patched
343 lines
11 KiB
C
343 lines
11 KiB
C
#ifndef _I830_DRM_H_
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#define _I830_DRM_H_
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/* WARNING: These defines must be the same as what the Xserver uses.
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* if you change them, you must change the defines in the Xserver.
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*
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* KW: Actually, you can't ever change them because doing so would
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* break backwards compatibility.
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*/
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#ifndef _I830_DEFINES_
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#define _I830_DEFINES_
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#define I830_DMA_BUF_ORDER 12
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#define I830_DMA_BUF_SZ (1<<I830_DMA_BUF_ORDER)
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#define I830_DMA_BUF_NR 256
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#define I830_NR_SAREA_CLIPRECTS 8
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/* Each region is a minimum of 64k, and there are at most 64 of them.
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*/
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#define I830_NR_TEX_REGIONS 64
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#define I830_LOG_MIN_TEX_REGION_SIZE 16
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/* KW: These aren't correct but someone set them to two and then
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* released the module. Now we can't change them as doing so would
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* break backwards compatibility.
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*/
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#define I830_TEXTURE_COUNT 2
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#define I830_TEXBLEND_COUNT I830_TEXTURE_COUNT
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#define I830_TEXBLEND_SIZE 12 /* (4 args + op) * 2 + COLOR_FACTOR */
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#define I830_UPLOAD_CTX 0x1
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#define I830_UPLOAD_BUFFERS 0x2
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#define I830_UPLOAD_CLIPRECTS 0x4
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#define I830_UPLOAD_TEX0_IMAGE 0x100 /* handled clientside */
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#define I830_UPLOAD_TEX0_CUBE 0x200 /* handled clientside */
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#define I830_UPLOAD_TEX1_IMAGE 0x400 /* handled clientside */
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#define I830_UPLOAD_TEX1_CUBE 0x800 /* handled clientside */
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#define I830_UPLOAD_TEX2_IMAGE 0x1000 /* handled clientside */
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#define I830_UPLOAD_TEX2_CUBE 0x2000 /* handled clientside */
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#define I830_UPLOAD_TEX3_IMAGE 0x4000 /* handled clientside */
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#define I830_UPLOAD_TEX3_CUBE 0x8000 /* handled clientside */
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#define I830_UPLOAD_TEX_N_IMAGE(n) (0x100 << (n * 2))
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#define I830_UPLOAD_TEX_N_CUBE(n) (0x200 << (n * 2))
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#define I830_UPLOAD_TEXIMAGE_MASK 0xff00
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#define I830_UPLOAD_TEX0 0x10000
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#define I830_UPLOAD_TEX1 0x20000
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#define I830_UPLOAD_TEX2 0x40000
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#define I830_UPLOAD_TEX3 0x80000
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#define I830_UPLOAD_TEX_N(n) (0x10000 << (n))
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#define I830_UPLOAD_TEX_MASK 0xf0000
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#define I830_UPLOAD_TEXBLEND0 0x100000
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#define I830_UPLOAD_TEXBLEND1 0x200000
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#define I830_UPLOAD_TEXBLEND2 0x400000
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#define I830_UPLOAD_TEXBLEND3 0x800000
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#define I830_UPLOAD_TEXBLEND_N(n) (0x100000 << (n))
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#define I830_UPLOAD_TEXBLEND_MASK 0xf00000
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#define I830_UPLOAD_TEX_PALETTE_N(n) (0x1000000 << (n))
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#define I830_UPLOAD_TEX_PALETTE_SHARED 0x4000000
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#define I830_UPLOAD_STIPPLE 0x8000000
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/* Indices into buf.Setup where various bits of state are mirrored per
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* context and per buffer. These can be fired at the card as a unit,
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* or in a piecewise fashion as required.
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*/
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/* Destbuffer state
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* - backbuffer linear offset and pitch -- invarient in the current dri
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* - zbuffer linear offset and pitch -- also invarient
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* - drawing origin in back and depth buffers.
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*
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* Keep the depth/back buffer state here to accommodate private buffers
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* in the future.
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*/
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#define I830_DESTREG_CBUFADDR 0
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#define I830_DESTREG_DBUFADDR 1
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#define I830_DESTREG_DV0 2
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#define I830_DESTREG_DV1 3
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#define I830_DESTREG_SENABLE 4
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#define I830_DESTREG_SR0 5
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#define I830_DESTREG_SR1 6
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#define I830_DESTREG_SR2 7
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#define I830_DESTREG_DR0 8
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#define I830_DESTREG_DR1 9
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#define I830_DESTREG_DR2 10
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#define I830_DESTREG_DR3 11
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#define I830_DESTREG_DR4 12
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#define I830_DEST_SETUP_SIZE 13
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/* Context state
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*/
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#define I830_CTXREG_STATE1 0
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#define I830_CTXREG_STATE2 1
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#define I830_CTXREG_STATE3 2
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#define I830_CTXREG_STATE4 3
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#define I830_CTXREG_STATE5 4
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#define I830_CTXREG_IALPHAB 5
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#define I830_CTXREG_STENCILTST 6
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#define I830_CTXREG_ENABLES_1 7
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#define I830_CTXREG_ENABLES_2 8
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#define I830_CTXREG_AA 9
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#define I830_CTXREG_FOGCOLOR 10
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#define I830_CTXREG_BLENDCOLR0 11
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#define I830_CTXREG_BLENDCOLR 12 /* Dword 1 of 2 dword command */
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#define I830_CTXREG_VF 13
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#define I830_CTXREG_VF2 14
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#define I830_CTXREG_MCSB0 15
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#define I830_CTXREG_MCSB1 16
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#define I830_CTX_SETUP_SIZE 17
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/* 1.3: Stipple state
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*/
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#define I830_STPREG_ST0 0
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#define I830_STPREG_ST1 1
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#define I830_STP_SETUP_SIZE 2
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/* Texture state (per tex unit)
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*/
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#define I830_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (6 dwords) */
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#define I830_TEXREG_MI1 1
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#define I830_TEXREG_MI2 2
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#define I830_TEXREG_MI3 3
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#define I830_TEXREG_MI4 4
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#define I830_TEXREG_MI5 5
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#define I830_TEXREG_MF 6 /* GFX_OP_MAP_FILTER */
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#define I830_TEXREG_MLC 7 /* GFX_OP_MAP_LOD_CTL */
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#define I830_TEXREG_MLL 8 /* GFX_OP_MAP_LOD_LIMITS */
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#define I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS */
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#define I830_TEX_SETUP_SIZE 10
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#define I830_TEXREG_TM0LI 0 /* load immediate 2 texture map n */
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#define I830_TEXREG_TM0S0 1
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#define I830_TEXREG_TM0S1 2
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#define I830_TEXREG_TM0S2 3
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#define I830_TEXREG_TM0S3 4
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#define I830_TEXREG_TM0S4 5
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#define I830_TEXREG_NOP0 6 /* noop */
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#define I830_TEXREG_NOP1 7 /* noop */
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#define I830_TEXREG_NOP2 8 /* noop */
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#define __I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS -- shared */
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#define __I830_TEX_SETUP_SIZE 10
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#define I830_FRONT 0x1
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#define I830_BACK 0x2
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#define I830_DEPTH 0x4
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#endif /* _I830_DEFINES_ */
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typedef struct _drm_i830_init {
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enum {
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I830_INIT_DMA = 0x01,
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I830_CLEANUP_DMA = 0x02
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} func;
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unsigned int mmio_offset;
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unsigned int buffers_offset;
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int sarea_priv_offset;
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unsigned int ring_start;
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unsigned int ring_end;
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unsigned int ring_size;
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unsigned int front_offset;
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unsigned int back_offset;
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unsigned int depth_offset;
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unsigned int w;
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unsigned int h;
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unsigned int pitch;
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unsigned int pitch_bits;
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unsigned int back_pitch;
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unsigned int depth_pitch;
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unsigned int cpp;
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} drm_i830_init_t;
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/* Warning: If you change the SAREA structure you must change the Xserver
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* structure as well */
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typedef struct _drm_i830_tex_region {
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unsigned char next, prev; /* indices to form a circular LRU */
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unsigned char in_use; /* owned by a client, or free? */
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int age; /* tracked by clients to update local LRU's */
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} drm_i830_tex_region_t;
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typedef struct _drm_i830_sarea {
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unsigned int ContextState[I830_CTX_SETUP_SIZE];
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unsigned int BufferState[I830_DEST_SETUP_SIZE];
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unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE];
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unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE];
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unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT];
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unsigned int Palette[2][256];
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unsigned int dirty;
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unsigned int nbox;
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struct drm_clip_rect boxes[I830_NR_SAREA_CLIPRECTS];
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/* Maintain an LRU of contiguous regions of texture space. If
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* you think you own a region of texture memory, and it has an
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* age different to the one you set, then you are mistaken and
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* it has been stolen by another client. If global texAge
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* hasn't changed, there is no need to walk the list.
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*
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* These regions can be used as a proxy for the fine-grained
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* texture information of other clients - by maintaining them
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* in the same lru which is used to age their own textures,
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* clients have an approximate lru for the whole of global
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* texture space, and can make informed decisions as to which
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* areas to kick out. There is no need to choose whether to
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* kick out your own texture or someone else's - simply eject
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* them all in LRU order.
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*/
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drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS + 1];
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/* Last elt is sentinal */
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int texAge; /* last time texture was uploaded */
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int last_enqueue; /* last time a buffer was enqueued */
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int last_dispatch; /* age of the most recently dispatched buffer */
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int last_quiescent; /* */
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int ctxOwner; /* last context to upload state */
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int vertex_prim;
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int pf_enabled; /* is pageflipping allowed? */
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int pf_active;
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int pf_current_page; /* which buffer is being displayed? */
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int perf_boxes; /* performance boxes to be displayed */
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/* Here's the state for texunits 2,3:
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*/
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unsigned int TexState2[I830_TEX_SETUP_SIZE];
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unsigned int TexBlendState2[I830_TEXBLEND_SIZE];
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unsigned int TexBlendStateWordsUsed2;
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unsigned int TexState3[I830_TEX_SETUP_SIZE];
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unsigned int TexBlendState3[I830_TEXBLEND_SIZE];
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unsigned int TexBlendStateWordsUsed3;
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unsigned int StippleState[I830_STP_SETUP_SIZE];
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} drm_i830_sarea_t;
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/* Flags for perf_boxes
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*/
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#define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */
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#define I830_BOX_FLIP 0x2 /* populated by kernel */
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#define I830_BOX_WAIT 0x4 /* populated by kernel & client */
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#define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */
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#define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */
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/* I830 specific ioctls
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* The device specific ioctl range is 0x40 to 0x79.
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*/
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#define DRM_I830_INIT 0x00
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#define DRM_I830_VERTEX 0x01
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#define DRM_I830_CLEAR 0x02
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#define DRM_I830_FLUSH 0x03
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#define DRM_I830_GETAGE 0x04
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#define DRM_I830_GETBUF 0x05
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#define DRM_I830_SWAP 0x06
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#define DRM_I830_COPY 0x07
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#define DRM_I830_DOCOPY 0x08
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#define DRM_I830_FLIP 0x09
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#define DRM_I830_IRQ_EMIT 0x0a
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#define DRM_I830_IRQ_WAIT 0x0b
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#define DRM_I830_GETPARAM 0x0c
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#define DRM_I830_SETPARAM 0x0d
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#define DRM_IOCTL_I830_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_INIT, drm_i830_init_t)
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#define DRM_IOCTL_I830_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_VERTEX, drm_i830_vertex_t)
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#define DRM_IOCTL_I830_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_CLEAR, drm_i830_clear_t)
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#define DRM_IOCTL_I830_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_FLUSH)
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#define DRM_IOCTL_I830_GETAGE DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_GETAGE)
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#define DRM_IOCTL_I830_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_GETBUF, drm_i830_dma_t)
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#define DRM_IOCTL_I830_SWAP DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_SWAP)
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#define DRM_IOCTL_I830_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_COPY, drm_i830_copy_t)
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#define DRM_IOCTL_I830_DOCOPY DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_DOCOPY)
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#define DRM_IOCTL_I830_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_FLIP)
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#define DRM_IOCTL_I830_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_IRQ_EMIT, drm_i830_irq_emit_t)
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#define DRM_IOCTL_I830_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_IRQ_WAIT, drm_i830_irq_wait_t)
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#define DRM_IOCTL_I830_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_GETPARAM, drm_i830_getparam_t)
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#define DRM_IOCTL_I830_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_SETPARAM, drm_i830_setparam_t)
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typedef struct _drm_i830_clear {
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int clear_color;
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int clear_depth;
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int flags;
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unsigned int clear_colormask;
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unsigned int clear_depthmask;
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} drm_i830_clear_t;
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/* These may be placeholders if we have more cliprects than
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* I830_NR_SAREA_CLIPRECTS. In that case, the client sets discard to
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* false, indicating that the buffer will be dispatched again with a
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* new set of cliprects.
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*/
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typedef struct _drm_i830_vertex {
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int idx; /* buffer index */
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int used; /* nr bytes in use */
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int discard; /* client is finished with the buffer? */
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} drm_i830_vertex_t;
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typedef struct _drm_i830_copy_t {
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int idx; /* buffer index */
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int used; /* nr bytes in use */
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void __user *address; /* Address to copy from */
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} drm_i830_copy_t;
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typedef struct drm_i830_dma {
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void __user *virtual;
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int request_idx;
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int request_size;
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int granted;
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} drm_i830_dma_t;
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/* 1.3: Userspace can request & wait on irq's:
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*/
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typedef struct drm_i830_irq_emit {
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int __user *irq_seq;
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} drm_i830_irq_emit_t;
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typedef struct drm_i830_irq_wait {
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int irq_seq;
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} drm_i830_irq_wait_t;
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/* 1.3: New ioctl to query kernel params:
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*/
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#define I830_PARAM_IRQ_ACTIVE 1
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typedef struct drm_i830_getparam {
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int param;
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int __user *value;
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} drm_i830_getparam_t;
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/* 1.3: New ioctl to set kernel params:
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*/
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#define I830_SETPARAM_USE_MI_BATCHBUFFER_START 1
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typedef struct drm_i830_setparam {
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int param;
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int value;
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} drm_i830_setparam_t;
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#endif /* _I830_DRM_H_ */
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