forked from luck/tmp_suning_uos_patched
a43efddc3b
This patch removes all global data from common s5p gpio interrupt handler code. This enables to reuse this code on EXYNOS4 platform. Instead of global data (IRQ_GPIOINT interrupt number, S5P_GPIOINT_GROUP_MAXNR groups count), a s5p_register_gpioint_bank() function is introduced. It is aimed to be called from gpiolib init. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
356 lines
7.3 KiB
C
356 lines
7.3 KiB
C
/* linux/arch/arm/mach-s5pc100/gpiolib.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Copyright 2009 Samsung Electronics Co
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* S5PC100 - GPIOlib support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <mach/map.h>
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#include <mach/regs-gpio.h>
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#include <plat/gpio-core.h>
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#include <plat/gpio-cfg.h>
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#include <plat/gpio-cfg-helpers.h>
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/* S5PC100 GPIO bank summary:
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*
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* Bank GPIOs Style INT Type
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* A0 8 4Bit GPIO_INT0
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* A1 5 4Bit GPIO_INT1
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* B 8 4Bit GPIO_INT2
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* C 5 4Bit GPIO_INT3
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* D 7 4Bit GPIO_INT4
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* E0 8 4Bit GPIO_INT5
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* E1 6 4Bit GPIO_INT6
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* F0 8 4Bit GPIO_INT7
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* F1 8 4Bit GPIO_INT8
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* F2 8 4Bit GPIO_INT9
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* F3 4 4Bit GPIO_INT10
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* G0 8 4Bit GPIO_INT11
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* G1 3 4Bit GPIO_INT12
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* G2 7 4Bit GPIO_INT13
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* G3 7 4Bit GPIO_INT14
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* H0 8 4Bit WKUP_INT
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* H1 8 4Bit WKUP_INT
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* H2 8 4Bit WKUP_INT
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* H3 8 4Bit WKUP_INT
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* I 8 4Bit GPIO_INT15
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* J0 8 4Bit GPIO_INT16
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* J1 5 4Bit GPIO_INT17
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* J2 8 4Bit GPIO_INT18
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* J3 8 4Bit GPIO_INT19
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* J4 4 4Bit GPIO_INT20
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* K0 8 4Bit None
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* K1 6 4Bit None
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* K2 8 4Bit None
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* K3 8 4Bit None
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* L0 8 4Bit None
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* L1 8 4Bit None
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* L2 8 4Bit None
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* L3 8 4Bit None
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*/
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static struct s3c_gpio_cfg gpio_cfg = {
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_cfg gpio_cfg_eint = {
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.cfg_eint = 0xf,
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_cfg gpio_cfg_noint = {
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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/*
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* GPIO bank's base address given the index of the bank in the
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* list of all gpio banks.
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*/
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#define S5PC100_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20))
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/*
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* Following are the gpio banks in S5PC100.
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*
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* The 'config' member when left to NULL, is initialized to the default
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* structure gpio_cfg in the init function below.
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*
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* The 'base' member is also initialized in the init function below.
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* Note: The initialization of 'base' member of s3c_gpio_chip structure
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* uses the above macro and depends on the banks being listed in order here.
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*/
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static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
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{
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.chip = {
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.base = S5PC100_GPA0(0),
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.ngpio = S5PC100_GPIO_A0_NR,
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.label = "GPA0",
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},
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}, {
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.chip = {
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.base = S5PC100_GPA1(0),
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.ngpio = S5PC100_GPIO_A1_NR,
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.label = "GPA1",
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},
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}, {
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.chip = {
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.base = S5PC100_GPB(0),
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.ngpio = S5PC100_GPIO_B_NR,
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.label = "GPB",
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},
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}, {
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.chip = {
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.base = S5PC100_GPC(0),
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.ngpio = S5PC100_GPIO_C_NR,
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.label = "GPC",
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},
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}, {
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.chip = {
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.base = S5PC100_GPD(0),
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.ngpio = S5PC100_GPIO_D_NR,
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.label = "GPD",
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},
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}, {
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.chip = {
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.base = S5PC100_GPE0(0),
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.ngpio = S5PC100_GPIO_E0_NR,
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.label = "GPE0",
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},
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}, {
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.chip = {
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.base = S5PC100_GPE1(0),
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.ngpio = S5PC100_GPIO_E1_NR,
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.label = "GPE1",
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},
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}, {
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.chip = {
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.base = S5PC100_GPF0(0),
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.ngpio = S5PC100_GPIO_F0_NR,
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.label = "GPF0",
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},
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}, {
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.chip = {
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.base = S5PC100_GPF1(0),
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.ngpio = S5PC100_GPIO_F1_NR,
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.label = "GPF1",
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},
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}, {
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.chip = {
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.base = S5PC100_GPF2(0),
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.ngpio = S5PC100_GPIO_F2_NR,
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.label = "GPF2",
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},
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}, {
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.chip = {
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.base = S5PC100_GPF3(0),
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.ngpio = S5PC100_GPIO_F3_NR,
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.label = "GPF3",
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},
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}, {
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.chip = {
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.base = S5PC100_GPG0(0),
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.ngpio = S5PC100_GPIO_G0_NR,
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.label = "GPG0",
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},
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}, {
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.chip = {
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.base = S5PC100_GPG1(0),
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.ngpio = S5PC100_GPIO_G1_NR,
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.label = "GPG1",
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},
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}, {
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.chip = {
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.base = S5PC100_GPG2(0),
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.ngpio = S5PC100_GPIO_G2_NR,
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.label = "GPG2",
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},
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}, {
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.chip = {
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.base = S5PC100_GPG3(0),
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.ngpio = S5PC100_GPIO_G3_NR,
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.label = "GPG3",
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},
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}, {
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.chip = {
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.base = S5PC100_GPI(0),
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.ngpio = S5PC100_GPIO_I_NR,
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.label = "GPI",
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},
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}, {
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.chip = {
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.base = S5PC100_GPJ0(0),
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.ngpio = S5PC100_GPIO_J0_NR,
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.label = "GPJ0",
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},
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}, {
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.chip = {
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.base = S5PC100_GPJ1(0),
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.ngpio = S5PC100_GPIO_J1_NR,
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.label = "GPJ1",
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},
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}, {
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.chip = {
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.base = S5PC100_GPJ2(0),
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.ngpio = S5PC100_GPIO_J2_NR,
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.label = "GPJ2",
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},
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}, {
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.chip = {
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.base = S5PC100_GPJ3(0),
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.ngpio = S5PC100_GPIO_J3_NR,
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.label = "GPJ3",
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},
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}, {
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.chip = {
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.base = S5PC100_GPJ4(0),
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.ngpio = S5PC100_GPIO_J4_NR,
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.label = "GPJ4",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = S5PC100_GPK0(0),
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.ngpio = S5PC100_GPIO_K0_NR,
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.label = "GPK0",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = S5PC100_GPK1(0),
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.ngpio = S5PC100_GPIO_K1_NR,
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.label = "GPK1",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = S5PC100_GPK2(0),
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.ngpio = S5PC100_GPIO_K2_NR,
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.label = "GPK2",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = S5PC100_GPK3(0),
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.ngpio = S5PC100_GPIO_K3_NR,
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.label = "GPK3",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = S5PC100_GPL0(0),
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.ngpio = S5PC100_GPIO_L0_NR,
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.label = "GPL0",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = S5PC100_GPL1(0),
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.ngpio = S5PC100_GPIO_L1_NR,
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.label = "GPL1",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = S5PC100_GPL2(0),
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.ngpio = S5PC100_GPIO_L2_NR,
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.label = "GPL2",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = S5PC100_GPL3(0),
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.ngpio = S5PC100_GPIO_L3_NR,
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.label = "GPL3",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = S5PC100_GPL4(0),
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.ngpio = S5PC100_GPIO_L4_NR,
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.label = "GPL4",
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC00),
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.config = &gpio_cfg_eint,
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.irq_base = IRQ_EINT(0),
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.chip = {
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.base = S5PC100_GPH0(0),
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.ngpio = S5PC100_GPIO_H0_NR,
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.label = "GPH0",
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.to_irq = samsung_gpiolib_to_irq,
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC20),
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.config = &gpio_cfg_eint,
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.irq_base = IRQ_EINT(8),
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.chip = {
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.base = S5PC100_GPH1(0),
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.ngpio = S5PC100_GPIO_H1_NR,
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.label = "GPH1",
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.to_irq = samsung_gpiolib_to_irq,
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC40),
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.config = &gpio_cfg_eint,
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.irq_base = IRQ_EINT(16),
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.chip = {
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.base = S5PC100_GPH2(0),
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.ngpio = S5PC100_GPIO_H2_NR,
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.label = "GPH2",
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.to_irq = samsung_gpiolib_to_irq,
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC60),
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.config = &gpio_cfg_eint,
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.irq_base = IRQ_EINT(24),
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.chip = {
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.base = S5PC100_GPH3(0),
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.ngpio = S5PC100_GPIO_H3_NR,
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.label = "GPH3",
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.to_irq = samsung_gpiolib_to_irq,
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},
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},
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};
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static __init int s5pc100_gpiolib_init(void)
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{
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struct s3c_gpio_chip *chip = s5pc100_gpio_chips;
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int nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
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int gpioint_group = 0;
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int i;
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for (i = 0; i < nr_chips; i++, chip++) {
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if (chip->config == NULL) {
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chip->config = &gpio_cfg;
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chip->group = gpioint_group++;
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}
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if (chip->base == NULL)
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chip->base = S5PC100_BANK_BASE(i);
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}
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samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips);
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s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
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return 0;
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}
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core_initcall(s5pc100_gpiolib_init);
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