Sifan Naeem c7b0a7c107 i2c: img-scb: add handle for Master halt interrupt ... Master halt is issued after each byte of a transaction is processed in IP version 3.3. Master halt will stall the bus by holding the SCK line low until the halt bit in the scb_general_control is cleared. After the last byte of a transfer is processed we can use the Master Halt interrupt to facilitate a repeated start transfer without issuing a stop bit. Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com> Reviewed-by: James Hartley <james.hartley@imgtec.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>		2016-01-02 22:04:55 +01:00
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algos	i2c: algo-bit: add I2C_AQ_NO_CLK_STRETCH	2015-11-30 18:37:25 +01:00
busses	i2c: img-scb: add handle for Master halt interrupt	2016-01-02 22:04:55 +01:00
muxes
i2c-boardinfo.c
i2c-core.c	i2c: make i2c_parse_fw_timings() always visible	2015-12-17 20:36:39 +01:00
i2c-core.h
i2c-dev.c
i2c-mux.c
i2c-slave-eeprom.c
i2c-smbus.c
i2c-stub.c
Kconfig
Makefile