forked from luck/tmp_suning_uos_patched
e28b003136
This adds a platform specific spu management abstraction and the coresponding routines to support the IBM Cell Blade. It also removes the hypervisor only resources that were included in struct spu. Three new platform specific routines are introduced, spu_enumerate_spus(), spu_create_spu() and spu_destroy_spu(). The underlying design uses a new type, struct spu_management_ops, to hold function pointers that the platform setup code is expected to initialize to instances appropriate to that platform. For the IBM Cell Blade support, I put the hypervisor only resources that were in struct spu into a platform specific data structure struct spu_pdata. Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
224 lines
5.0 KiB
C
224 lines
5.0 KiB
C
/*
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* linux/arch/powerpc/platforms/cell/cell_setup.c
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*
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* Copyright (C) 1995 Linus Torvalds
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* Adapted from 'alpha' version by Gary Thomas
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* Modified by Cort Dougan (cort@cs.nmt.edu)
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* Modified by PPC64 Team, IBM Corp
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* Modified by Cell Team, IBM Deutschland Entwicklung GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/slab.h>
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#include <linux/user.h>
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#include <linux/reboot.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/console.h>
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#include <linux/mutex.h>
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#include <linux/memory_hotplug.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/kexec.h>
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#include <asm/pgtable.h>
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#include <asm/prom.h>
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#include <asm/rtas.h>
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#include <asm/pci-bridge.h>
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#include <asm/iommu.h>
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#include <asm/dma.h>
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#include <asm/machdep.h>
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#include <asm/time.h>
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#include <asm/nvram.h>
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#include <asm/cputable.h>
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#include <asm/ppc-pci.h>
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#include <asm/irq.h>
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#include <asm/spu.h>
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#include <asm/spu_priv1.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <asm/of_platform.h>
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#include "interrupt.h"
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#include "cbe_regs.h"
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#include "pervasive.h"
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#include "ras.h"
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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static void cell_show_cpuinfo(struct seq_file *m)
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{
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struct device_node *root;
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const char *model = "";
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root = of_find_node_by_path("/");
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if (root)
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model = get_property(root, "model", NULL);
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seq_printf(m, "machine\t\t: CHRP %s\n", model);
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of_node_put(root);
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}
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static void cell_progress(char *s, unsigned short hex)
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{
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printk("*** %04x : %s\n", hex, s ? s : "");
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}
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static int __init cell_publish_devices(void)
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{
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if (!machine_is(cell))
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return 0;
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/* Publish OF platform devices for southbridge IOs */
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of_platform_bus_probe(NULL, NULL, NULL);
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return 0;
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}
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device_initcall(cell_publish_devices);
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static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc)
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{
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struct mpic *mpic = desc->handler_data;
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unsigned int virq;
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virq = mpic_get_one_irq(mpic);
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if (virq != NO_IRQ)
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generic_handle_irq(virq);
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desc->chip->eoi(irq);
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}
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static void __init mpic_init_IRQ(void)
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{
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struct device_node *dn;
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struct mpic *mpic;
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unsigned int virq;
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for (dn = NULL;
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(dn = of_find_node_by_name(dn, "interrupt-controller"));) {
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if (!device_is_compatible(dn, "CBEA,platform-open-pic"))
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continue;
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/* The MPIC driver will get everything it needs from the
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* device-tree, just pass 0 to all arguments
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*/
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mpic = mpic_alloc(dn, 0, 0, 0, 0, " MPIC ");
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if (mpic == NULL)
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continue;
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mpic_init(mpic);
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virq = irq_of_parse_and_map(dn, 0);
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if (virq == NO_IRQ)
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continue;
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printk(KERN_INFO "%s : hooking up to IRQ %d\n",
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dn->full_name, virq);
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set_irq_data(virq, mpic);
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set_irq_chained_handler(virq, cell_mpic_cascade);
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}
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}
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static void __init cell_init_irq(void)
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{
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iic_init_IRQ();
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spider_init_IRQ();
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mpic_init_IRQ();
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}
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static void __init cell_setup_arch(void)
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{
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#ifdef CONFIG_SPU_BASE
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spu_priv1_ops = &spu_priv1_mmio_ops;
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spu_management_ops = &spu_management_of_ops;
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#endif
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cbe_regs_init();
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#ifdef CONFIG_CBE_RAS
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cbe_ras_init();
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#endif
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#ifdef CONFIG_SMP
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smp_init_cell();
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#endif
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/* init to some ~sane value until calibrate_delay() runs */
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loops_per_jiffy = 50000000;
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if (ROOT_DEV == 0) {
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printk("No ramdisk, default root is /dev/hda2\n");
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ROOT_DEV = Root_HDA2;
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}
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/* Find and initialize PCI host bridges */
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init_pci_config_tokens();
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find_and_init_phbs();
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cbe_pervasive_init();
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#ifdef CONFIG_DUMMY_CONSOLE
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conswitchp = &dummy_con;
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#endif
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mmio_nvram_init();
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}
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static int __init cell_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (!of_flat_dt_is_compatible(root, "IBM,CBEA") &&
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!of_flat_dt_is_compatible(root, "IBM,CPBW-1.0"))
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return 0;
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hpte_init_native();
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return 1;
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}
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/*
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* Cell has no legacy IO; anything calling this function has to
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* fail or bad things will happen
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*/
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static int cell_check_legacy_ioport(unsigned int baseport)
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{
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return -ENODEV;
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}
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define_machine(cell) {
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.name = "Cell",
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.probe = cell_probe,
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.setup_arch = cell_setup_arch,
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.show_cpuinfo = cell_show_cpuinfo,
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.restart = rtas_restart,
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.power_off = rtas_power_off,
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.halt = rtas_halt,
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.get_boot_time = rtas_get_boot_time,
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.get_rtc_time = rtas_get_rtc_time,
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.set_rtc_time = rtas_set_rtc_time,
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.calibrate_decr = generic_calibrate_decr,
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.check_legacy_ioport = cell_check_legacy_ioport,
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.progress = cell_progress,
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.init_IRQ = cell_init_irq,
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.pci_setup_phb = rtas_setup_phb,
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#ifdef CONFIG_KEXEC
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.machine_kexec = default_machine_kexec,
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.machine_kexec_prepare = default_machine_kexec_prepare,
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.machine_crash_shutdown = default_machine_crash_shutdown,
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#endif
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};
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