forked from luck/tmp_suning_uos_patched
a50808b6c4
Add register definitions for Freescale STMP 378n boards Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
88 lines
3.2 KiB
C
88 lines
3.2 KiB
C
/*
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* stmp378x: DCP register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define REGS_DCP_BASE (STMP3XXX_REGS_BASE + 0x28000)
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#define REGS_DCP_PHYS 0x80028000
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#define REGS_DCP_SIZE 0x2000
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#define HW_DCP_CTRL 0x0
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#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF
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#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0
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#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000
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#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000
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#define BM_DCP_CTRL_CLKGATE 0x40000000
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#define BM_DCP_CTRL_SFTRST 0x80000000
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#define HW_DCP_STAT 0x10
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#define BM_DCP_STAT_IRQ 0x0000000F
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#define BP_DCP_STAT_IRQ 0
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#define HW_DCP_CHANNELCTRL 0x20
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#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF
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#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0
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#define HW_DCP_CONTEXT 0x50
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#define BM_DCP_PACKET1_INTERRUPT 0x00000001
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#define BP_DCP_PACKET1_INTERRUPT 0
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#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002
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#define BM_DCP_PACKET1_CHAIN 0x00000004
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#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008
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#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020
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#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040
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#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100
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#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200
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#define BM_DCP_PACKET1_OTP_KEY 0x00000400
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#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800
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#define BM_DCP_PACKET1_HASH_INIT 0x00001000
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#define BM_DCP_PACKET1_HASH_TERM 0x00002000
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#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F
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#define BP_DCP_PACKET2_CIPHER_SELECT 0
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#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0
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#define BP_DCP_PACKET2_CIPHER_MODE 4
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#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00
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#define BP_DCP_PACKET2_KEY_SELECT 8
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#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000
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#define BP_DCP_PACKET2_HASH_SELECT 16
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#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000
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#define BP_DCP_PACKET2_CIPHER_CFG 24
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#define HW_DCP_CH0CMDPTR (0x100 + 0 * 0x40)
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#define HW_DCP_CH1CMDPTR (0x100 + 1 * 0x40)
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#define HW_DCP_CH2CMDPTR (0x100 + 2 * 0x40)
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#define HW_DCP_CH3CMDPTR (0x100 + 3 * 0x40)
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#define HW_DCP_CHnCMDPTR 0x100
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#define HW_DCP_CH0SEMA (0x110 + 0 * 0x40)
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#define HW_DCP_CH1SEMA (0x110 + 1 * 0x40)
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#define HW_DCP_CH2SEMA (0x110 + 2 * 0x40)
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#define HW_DCP_CH3SEMA (0x110 + 3 * 0x40)
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#define HW_DCP_CHnSEMA 0x110
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#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF
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#define BP_DCP_CHnSEMA_INCREMENT 0
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#define HW_DCP_CH0STAT (0x120 + 0 * 0x40)
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#define HW_DCP_CH1STAT (0x120 + 1 * 0x40)
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#define HW_DCP_CH2STAT (0x120 + 2 * 0x40)
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#define HW_DCP_CH3STAT (0x120 + 3 * 0x40)
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#define HW_DCP_CHnSTAT 0x120
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