forked from luck/tmp_suning_uos_patched
8eb742a091
All shdma DMACs on ARM SoCs share certain register layout patterns, which are currently defined in arch/arm/mach-shmobile/include/mach/dma-register.h. That header is included by SoC-specific setup-*.c files to be used in DMAC platform data. That header, however, cannot be directly used by the driver. This patch copies those defines into a driver-local header to be used by Device Tree configurations. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
52 lines
1.2 KiB
C
52 lines
1.2 KiB
C
/*
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* Renesas SuperH DMA Engine support
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*
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* Copyright (C) 2013 Renesas Electronics, Inc.
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*
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* This is free software; you can redistribute it and/or modify it under the
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* terms of version 2 the GNU General Public License as published by the Free
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* Software Foundation.
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*/
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#ifndef SHDMA_ARM_H
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#define SHDMA_ARM_H
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#include "shdma.h"
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/* Transmit sizes and respective CHCR register values */
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enum {
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XMIT_SZ_8BIT = 0,
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XMIT_SZ_16BIT = 1,
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XMIT_SZ_32BIT = 2,
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XMIT_SZ_64BIT = 7,
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XMIT_SZ_128BIT = 3,
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XMIT_SZ_256BIT = 4,
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XMIT_SZ_512BIT = 5,
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};
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/* log2(size / 8) - used to calculate number of transfers */
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#define SH_DMAE_TS_SHIFT { \
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[XMIT_SZ_8BIT] = 0, \
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[XMIT_SZ_16BIT] = 1, \
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[XMIT_SZ_32BIT] = 2, \
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[XMIT_SZ_64BIT] = 3, \
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[XMIT_SZ_128BIT] = 4, \
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[XMIT_SZ_256BIT] = 5, \
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[XMIT_SZ_512BIT] = 6, \
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}
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#define TS_LOW_BIT 0x3 /* --xx */
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#define TS_HI_BIT 0xc /* xx-- */
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#define TS_LOW_SHIFT (3)
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#define TS_HI_SHIFT (20 - 2) /* 2 bits for shifted low TS */
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#define TS_INDEX2VAL(i) \
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((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\
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(((i) & TS_HI_BIT) << TS_HI_SHIFT))
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#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
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#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
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#endif
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