Fabrice Gasnier 6d4e1fed18 counter: stm32-timer-cnt: fix ceiling miss-alignment with reload register ... commit b14d72ac731753708a7c1a6b3657b9312b6f0042 upstream. Ceiling value may be miss-aligned with what's actually configured into the ARR register. This is seen after probe as currently the ARR value is zero, whereas ceiling value is set to the maximum. So: - reading ceiling reports zero - in case the counter gets enabled without any prior configuration, it won't count. - in case the function gets set by the user 1st, (priv->ceiling) is used. Fix it by getting rid of the cached "priv->ceiling" variable. Rather use the ARR register value directly by using regmap read or write when needed. There should be no drawback on performance as priv->ceiling isn't used in performance critical path. There's also no point in writing ARR while setting function (sms), so it can be safely removed. Fixes: ad29937e20 ("counter: Add STM32 Timer quadrature encoder") Suggested-by: William Breathitt Gray <vilhelm.gray@gmail.com> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Acked-by: William Breathitt Gray <vilhelm.gray@gmail.com> Cc: <Stable@vger.kernel.org> Link: https://lore.kernel.org/r/1614793789-10346-1-git-send-email-fabrice.gasnier@foss.st.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2021-03-25 09:04:16 +01:00
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104-quad-8.c	Linux 5.8-rc6	2020-07-20 09:37:31 +02:00
counter.c
ftm-quaddec.c
Kconfig	counter: Add microchip TCB capture counter	2020-07-20 13:04:40 +01:00
Makefile	counter: Add microchip TCB capture counter	2020-07-20 13:04:40 +01:00
microchip-tcb-capture.c	counter: microchip-tcb-capture: Fix CMR value check	2020-12-30 11:54:26 +01:00
stm32-lptimer-cnt.c
stm32-timer-cnt.c	counter: stm32-timer-cnt: fix ceiling miss-alignment with reload register	2021-03-25 09:04:16 +01:00
ti-eqep.c	counter:ti-eqep: remove floor	2021-01-27 11:55:12 +01:00