forked from luck/tmp_suning_uos_patched
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
528 lines
13 KiB
C
528 lines
13 KiB
C
/*
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* arch/ppc/platforms/mcpn765.c
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*
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* Board setup routines for the Motorola MCG MCPN765 cPCI Board.
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*
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* Author: Mark A. Greer
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* mgreer@mvista.com
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*
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* Modified by Randy Vinson (rvinson@mvista.com)
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*
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* 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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/*
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* This file adds support for the Motorola MCG MCPN765.
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*/
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#include <linux/config.h>
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/initrd.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/serial.h>
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#include <linux/tty.h> /* for linux/serial_core.h */
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#include <linux/serial_core.h>
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#include <linux/slab.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/time.h>
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#include <asm/dma.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/prom.h>
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#include <asm/smp.h>
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#include <asm/open_pic.h>
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#include <asm/i8259.h>
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#include <asm/todc.h>
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#include <asm/pci-bridge.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include <asm/bootinfo.h>
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#include <asm/hawk.h>
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#include <asm/kgdb.h>
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#include "mcpn765.h"
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static u_char mcpn765_openpic_initsenses[] __initdata = {
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(IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE),/* 16: i8259 cascade */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 17: COM1,2,3,4 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 18: Enet 1 (front) */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 19: HAWK WDT XXXX */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 20: 21554 bridge */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 21: cPCI INTA# */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 22: cPCI INTB# */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 23: cPCI INTC# */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 24: cPCI INTD# */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 25: PMC1 INTA#,PMC2 INTB#*/
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 26: PMC1 INTB#,PMC2 INTC#*/
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 27: PMC1 INTC#,PMC2 INTD#*/
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 28: PMC1 INTD#,PMC2 INTA#*/
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 29: Enet 2 (J3) */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 30: Abort Switch */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 31: RTC Alarm */
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};
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extern void mcpn765_set_VIA_IDE_native(void);
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extern u_int openpic_irq(void);
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extern char cmd_line[];
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extern void gen550_progress(char *, unsigned short);
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extern void gen550_init(int, struct uart_port *);
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int use_of_interrupt_tree = 0;
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static void mcpn765_halt(void);
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TODC_ALLOC();
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/*
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* Motorola MCG MCPN765 interrupt routing.
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*/
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static inline int
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mcpn765_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{ 14, 0, 0, 0 }, /* IDSEL 11 - have to manually set */
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{ 0, 0, 0, 0 }, /* IDSEL 12 - unused */
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{ 0, 0, 0, 0 }, /* IDSEL 13 - unused */
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{ 18, 0, 0, 0 }, /* IDSEL 14 - Enet 0 */
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{ 0, 0, 0, 0 }, /* IDSEL 15 - unused */
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{ 25, 26, 27, 28 }, /* IDSEL 16 - PMC Slot 1 */
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{ 28, 25, 26, 27 }, /* IDSEL 17 - PMC Slot 2 */
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{ 0, 0, 0, 0 }, /* IDSEL 18 - PMC 2B Connector XXXX */
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{ 29, 0, 0, 0 }, /* IDSEL 19 - Enet 1 */
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{ 20, 0, 0, 0 }, /* IDSEL 20 - 21554 cPCI bridge */
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};
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const long min_idsel = 11, max_idsel = 20, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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void __init
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mcpn765_set_VIA_IDE_legacy(void)
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{
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unsigned short vend, dev;
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early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
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early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
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if ((vend == PCI_VENDOR_ID_VIA) &&
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(dev == PCI_DEVICE_ID_VIA_82C586_1)) {
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unsigned char temp;
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/* put back original "standard" port base addresses */
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early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
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PCI_BASE_ADDRESS_0, 0x1f1);
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early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
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PCI_BASE_ADDRESS_1, 0x3f5);
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early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
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PCI_BASE_ADDRESS_2, 0x171);
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early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
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PCI_BASE_ADDRESS_3, 0x375);
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early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
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PCI_BASE_ADDRESS_4, 0xcc01);
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/* put into legacy mode */
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early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
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&temp);
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temp &= ~0x05;
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early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
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temp);
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}
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}
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void
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mcpn765_set_VIA_IDE_native(void)
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{
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unsigned short vend, dev;
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early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
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early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
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if ((vend == PCI_VENDOR_ID_VIA) &&
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(dev == PCI_DEVICE_ID_VIA_82C586_1)) {
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unsigned char temp;
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/* put into native mode */
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early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
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&temp);
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temp |= 0x05;
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early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
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temp);
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}
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}
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/*
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* Initialize the VIA 82c586b.
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*/
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static void __init
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mcpn765_setup_via_82c586b(void)
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{
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struct pci_dev *dev;
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u_char c;
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if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_82C586_0,
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NULL)) == NULL) {
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printk("No VIA ISA bridge found\n");
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mcpn765_halt();
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/* NOTREACHED */
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}
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/*
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* If the firmware left the EISA 4d0/4d1 ports enabled, make sure
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* IRQ 14 is set for edge.
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*/
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pci_read_config_byte(dev, 0x47, &c);
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if (c & (1<<5)) {
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c = inb(0x4d1);
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c &= ~(1<<6);
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outb(c, 0x4d1);
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}
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/* Disable PNP IRQ routing since we use the Hawk's MPIC */
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pci_write_config_dword(dev, 0x54, 0);
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pci_write_config_byte(dev, 0x58, 0);
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pci_dev_put(dev);
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if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_82C586_1,
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NULL)) == NULL) {
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printk("No VIA ISA bridge found\n");
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mcpn765_halt();
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/* NOTREACHED */
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}
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/*
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* PPCBug doesn't set the enable bits for the IDE device.
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* Turn them on now.
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*/
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pci_read_config_byte(dev, 0x40, &c);
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c |= 0x03;
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pci_write_config_byte(dev, 0x40, c);
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pci_dev_put(dev);
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return;
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}
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void __init
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mcpn765_pcibios_fixup(void)
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{
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/* Do MCPN765 board specific initialization. */
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mcpn765_setup_via_82c586b();
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}
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void __init
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mcpn765_find_bridges(void)
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{
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struct pci_controller *hose;
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hose = pcibios_alloc_controller();
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if (!hose)
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return;
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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hose->pci_mem_offset = MCPN765_PCI_PHY_MEM_OFFSET;
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pci_init_resource(&hose->io_resource,
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MCPN765_PCI_IO_START,
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MCPN765_PCI_IO_END,
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IORESOURCE_IO,
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"PCI host bridge");
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pci_init_resource(&hose->mem_resources[0],
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MCPN765_PCI_MEM_START,
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MCPN765_PCI_MEM_END,
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IORESOURCE_MEM,
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"PCI host bridge");
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hose->io_space.start = MCPN765_PCI_IO_START;
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hose->io_space.end = MCPN765_PCI_IO_END;
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hose->mem_space.start = MCPN765_PCI_MEM_START;
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hose->mem_space.end = MCPN765_PCI_MEM_END - HAWK_MPIC_SIZE;
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if (hawk_init(hose,
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MCPN765_HAWK_PPC_REG_BASE,
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MCPN765_PROC_PCI_MEM_START,
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MCPN765_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
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MCPN765_PROC_PCI_IO_START,
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MCPN765_PROC_PCI_IO_END,
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MCPN765_PCI_MEM_END - HAWK_MPIC_SIZE + 1) != 0) {
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printk("Could not initialize HAWK bridge\n");
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}
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/* VIA IDE BAR decoders are only 16-bits wide. PCI Auto Config
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* will reassign the bars outside of 16-bit I/O space, which will
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* "break" things. To prevent this, we'll set the IDE chip into
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* legacy mode and seed the bars with their legacy addresses (in 16-bit
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* I/O space). The Auto Config code will skip the IDE contoller in
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* legacy mode, so our bar values will stick.
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*/
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mcpn765_set_VIA_IDE_legacy();
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hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
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/* Now that we've got 16-bit addresses in the bars, we can switch the
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* IDE controller back into native mode so we can do "modern" resource
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* and interrupt management.
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*/
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mcpn765_set_VIA_IDE_native();
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ppc_md.pcibios_fixup = mcpn765_pcibios_fixup;
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ppc_md.pcibios_fixup_bus = NULL;
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = mcpn765_map_irq;
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return;
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}
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static void __init
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mcpn765_setup_arch(void)
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{
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struct pci_controller *hose;
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if ( ppc_md.progress )
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ppc_md.progress("mcpn765_setup_arch: enter", 0);
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loops_per_jiffy = 50000000 / HZ;
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_SDA2;
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#endif
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if ( ppc_md.progress )
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ppc_md.progress("mcpn765_setup_arch: find_bridges", 0);
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/* Lookup PCI host bridges */
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mcpn765_find_bridges();
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hose = pci_bus_to_hose(0);
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isa_io_base = (ulong)hose->io_base_virt;
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TODC_INIT(TODC_TYPE_MK48T37,
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(MCPN765_PHYS_NVRAM_AS0 - isa_io_base),
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(MCPN765_PHYS_NVRAM_AS1 - isa_io_base),
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(MCPN765_PHYS_NVRAM_DATA - isa_io_base),
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8);
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OpenPIC_InitSenses = mcpn765_openpic_initsenses;
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OpenPIC_NumInitSenses = sizeof(mcpn765_openpic_initsenses);
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printk("Motorola MCG MCPN765 cPCI Non-System Board\n");
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printk("MCPN765 port (MontaVista Software, Inc. (source@mvista.com))\n");
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if ( ppc_md.progress )
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ppc_md.progress("mcpn765_setup_arch: exit", 0);
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return;
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}
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static void __init
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mcpn765_init2(void)
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{
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request_region(0x00,0x20,"dma1");
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request_region(0x20,0x20,"pic1");
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request_region(0x40,0x20,"timer");
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request_region(0x80,0x10,"dma page reg");
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request_region(0xa0,0x20,"pic2");
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request_region(0xc0,0x20,"dma2");
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return;
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}
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/*
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* Interrupt setup and service.
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* Have MPIC on HAWK and cascaded 8259s on VIA 82586 cascaded to MPIC.
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*/
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static void __init
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mcpn765_init_IRQ(void)
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{
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int i;
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if ( ppc_md.progress )
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ppc_md.progress("init_irq: enter", 0);
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openpic_init(NUM_8259_INTERRUPTS);
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openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
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i8259_irq);
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for(i=0; i < NUM_8259_INTERRUPTS; i++)
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irq_desc[i].handler = &i8259_pic;
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i8259_init(0);
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if ( ppc_md.progress )
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ppc_md.progress("init_irq: exit", 0);
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return;
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}
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static u32
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mcpn765_irq_canonicalize(u32 irq)
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{
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if (irq == 2)
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return 9;
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else
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return irq;
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}
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static unsigned long __init
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mcpn765_find_end_of_memory(void)
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{
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return hawk_get_mem_size(MCPN765_HAWK_SMC_BASE);
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}
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static void __init
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mcpn765_map_io(void)
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{
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io_block_mapping(0xfe800000, 0xfe800000, 0x00800000, _PAGE_IO);
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}
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static void
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mcpn765_reset_board(void)
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{
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local_irq_disable();
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/* set VIA IDE controller into native mode */
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mcpn765_set_VIA_IDE_native();
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/* Set exception prefix high - to the firmware */
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_nmask_and_or_msr(0, MSR_IP);
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out_8((u_char *)MCPN765_BOARD_MODRST_REG, 0x01);
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return;
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}
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static void
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mcpn765_restart(char *cmd)
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{
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volatile ulong i = 10000000;
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mcpn765_reset_board();
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while (i-- > 0);
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panic("restart failed\n");
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}
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static void
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mcpn765_power_off(void)
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{
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mcpn765_halt();
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/* NOTREACHED */
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}
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static void
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mcpn765_halt(void)
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{
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local_irq_disable();
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while (1);
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/* NOTREACHED */
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}
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static int
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mcpn765_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "vendor\t\t: Motorola MCG\n");
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seq_printf(m, "machine\t\t: MCPN765\n");
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return 0;
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}
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/*
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* Set BAT 3 to map 0xf0000000 to end of physical memory space.
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*/
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static __inline__ void
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mcpn765_set_bat(void)
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{
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mb();
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mtspr(SPRN_DBAT1U, 0xfe8000fe);
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mtspr(SPRN_DBAT1L, 0xfe80002a);
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mb();
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}
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void __init
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platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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parse_bootinfo(find_bootinfo());
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/* Map in board regs, etc. */
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mcpn765_set_bat();
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isa_mem_base = MCPN765_ISA_MEM_BASE;
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pci_dram_offset = MCPN765_PCI_DRAM_OFFSET;
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ISA_DMA_THRESHOLD = 0x00ffffff;
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DMA_MODE_READ = 0x44;
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DMA_MODE_WRITE = 0x48;
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ppc_md.setup_arch = mcpn765_setup_arch;
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ppc_md.show_cpuinfo = mcpn765_show_cpuinfo;
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ppc_md.irq_canonicalize = mcpn765_irq_canonicalize;
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ppc_md.init_IRQ = mcpn765_init_IRQ;
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ppc_md.get_irq = openpic_get_irq;
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ppc_md.init = mcpn765_init2;
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|
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ppc_md.restart = mcpn765_restart;
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ppc_md.power_off = mcpn765_power_off;
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ppc_md.halt = mcpn765_halt;
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|
|
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ppc_md.find_end_of_memory = mcpn765_find_end_of_memory;
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ppc_md.setup_io_mappings = mcpn765_map_io;
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|
|
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ppc_md.time_init = todc_time_init;
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ppc_md.set_rtc_time = todc_set_rtc_time;
|
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ppc_md.get_rtc_time = todc_get_rtc_time;
|
|
ppc_md.calibrate_decr = todc_calibrate_decr;
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|
|
|
ppc_md.nvram_read_val = todc_m48txx_read_val;
|
|
ppc_md.nvram_write_val = todc_m48txx_write_val;
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|
|
|
ppc_md.heartbeat = NULL;
|
|
ppc_md.heartbeat_reset = 0;
|
|
ppc_md.heartbeat_count = 0;
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|
|
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#ifdef CONFIG_SERIAL_TEXT_DEBUG
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ppc_md.progress = gen550_progress;
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#endif
|
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#ifdef CONFIG_KGDB
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|
ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
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#endif
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|
|
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return;
|
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}
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