forked from luck/tmp_suning_uos_patched
d2d7c05210
This is a backport of Helge Deller's recent patch for wireless-dev.git Signed-off-by: Daniel Drake <dsd@gentoo.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
280 lines
8.3 KiB
C
280 lines
8.3 KiB
C
/* zd_rf_rfmd.c: Functions for the RFMD RF controller
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include "zd_rf.h"
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#include "zd_usb.h"
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#include "zd_chip.h"
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static const u32 rf2959_table[][2] = {
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RF_CHANNEL( 1) = { 0x181979, 0x1e6666 },
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RF_CHANNEL( 2) = { 0x181989, 0x1e6666 },
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RF_CHANNEL( 3) = { 0x181999, 0x1e6666 },
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RF_CHANNEL( 4) = { 0x1819a9, 0x1e6666 },
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RF_CHANNEL( 5) = { 0x1819b9, 0x1e6666 },
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RF_CHANNEL( 6) = { 0x1819c9, 0x1e6666 },
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RF_CHANNEL( 7) = { 0x1819d9, 0x1e6666 },
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RF_CHANNEL( 8) = { 0x1819e9, 0x1e6666 },
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RF_CHANNEL( 9) = { 0x1819f9, 0x1e6666 },
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RF_CHANNEL(10) = { 0x181a09, 0x1e6666 },
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RF_CHANNEL(11) = { 0x181a19, 0x1e6666 },
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RF_CHANNEL(12) = { 0x181a29, 0x1e6666 },
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RF_CHANNEL(13) = { 0x181a39, 0x1e6666 },
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RF_CHANNEL(14) = { 0x181a60, 0x1c0000 },
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};
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#if 0
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static int bits(u32 rw, int from, int to)
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{
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rw &= ~(0xffffffffU << (to+1));
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rw >>= from;
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return rw;
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}
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static int bit(u32 rw, int bit)
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{
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return bits(rw, bit, bit);
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}
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static void dump_regwrite(u32 rw)
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{
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int reg = bits(rw, 18, 22);
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int rw_flag = bits(rw, 23, 23);
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PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);
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switch (reg) {
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case 0:
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PDEBUG("reg0 CFG1 ref_sel %d hybernate %d rf_vco_reg_en %d"
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" if_vco_reg_en %d if_vga_en %d",
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bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
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bit(rw, 0));
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break;
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case 1:
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PDEBUG("reg1 IFPLL1 pll_en1 %d kv_en1 %d vtc_en1 %d lpf1 %d"
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" cpl1 %d pdp1 %d autocal_en1 %d ld_en1 %d ifloopr %d"
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" ifloopc %d dac1 %d",
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bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
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bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
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bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3));
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break;
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case 2:
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PDEBUG("reg2 IFPLL2 n1 %d num1 %d",
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bits(rw, 6, 17), bits(rw, 0, 5));
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break;
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case 3:
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PDEBUG("reg3 IFPLL3 num %d", bits(rw, 0, 17));
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break;
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case 4:
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PDEBUG("reg4 IFPLL4 dn1 %#04x ct_def1 %d kv_def1 %d",
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bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
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break;
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case 5:
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PDEBUG("reg5 RFPLL1 pll_en %d kv_en %d vtc_en %d lpf %d cpl %d"
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" pdp %d autocal_en %d ld_en %d rfloopr %d rfloopc %d"
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" dac %d",
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bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
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bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
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bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0,3));
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break;
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case 6:
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PDEBUG("reg6 RFPLL2 n %d num %d",
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bits(rw, 6, 17), bits(rw, 0, 5));
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break;
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case 7:
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PDEBUG("reg7 RFPLL3 num2 %d", bits(rw, 0, 17));
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break;
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case 8:
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PDEBUG("reg8 RFPLL4 dn %#06x ct_def %d kv_def %d",
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bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
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break;
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case 9:
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PDEBUG("reg9 CAL1 tvco %d tlock %d m_ct_value %d ld_window %d",
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bits(rw, 13, 17), bits(rw, 8, 12), bits(rw, 3, 7),
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bits(rw, 0, 2));
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break;
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case 10:
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PDEBUG("reg10 TXRX1 rxdcfbbyps %d pcontrol %d txvgc %d"
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" rxlpfbw %d txlpfbw %d txdiffmode %d txenmode %d"
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" intbiasen %d tybypass %d",
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bit(rw, 17), bits(rw, 15, 16), bits(rw, 10, 14),
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bits(rw, 7, 9), bits(rw, 4, 6), bit(rw, 3), bit(rw, 2),
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bit(rw, 1), bit(rw, 0));
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break;
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case 11:
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PDEBUG("reg11 PCNT1 mid_bias %d p_desired %d pc_offset %d"
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" tx_delay %d",
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bits(rw, 15, 17), bits(rw, 9, 14), bits(rw, 3, 8),
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bits(rw, 0, 2));
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break;
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case 12:
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PDEBUG("reg12 PCNT2 max_power %d mid_power %d min_power %d",
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bits(rw, 12, 17), bits(rw, 6, 11), bits(rw, 0, 5));
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break;
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case 13:
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PDEBUG("reg13 VCOT1 rfpll vco comp %d ifpll vco comp %d"
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" lobias %d if_biasbuf %d if_biasvco %d rf_biasbuf %d"
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" rf_biasvco %d",
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bit(rw, 17), bit(rw, 16), bit(rw, 15),
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bits(rw, 8, 9), bits(rw, 5, 7), bits(rw, 3, 4),
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bits(rw, 0, 2));
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break;
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case 14:
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PDEBUG("reg14 IQCAL rx_acal %d rx_pcal %d"
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" tx_acal %d tx_pcal %d",
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bits(rw, 13, 17), bits(rw, 9, 12), bits(rw, 4, 8),
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bits(rw, 0, 3));
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break;
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}
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}
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#endif /* 0 */
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static int rf2959_init_hw(struct zd_rf *rf)
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{
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int r;
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struct zd_chip *chip = zd_rf_to_chip(rf);
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static const struct zd_ioreq16 ioreqs[] = {
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{ CR2, 0x1E }, { CR9, 0x20 }, { CR10, 0x89 },
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{ CR11, 0x00 }, { CR15, 0xD0 }, { CR17, 0x68 },
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{ CR19, 0x4a }, { CR20, 0x0c }, { CR21, 0x0E },
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{ CR23, 0x48 },
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/* normal size for cca threshold */
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{ CR24, 0x14 },
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/* { CR24, 0x20 }, */
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{ CR26, 0x90 }, { CR27, 0x30 }, { CR29, 0x20 },
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{ CR31, 0xb2 }, { CR32, 0x43 }, { CR33, 0x28 },
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{ CR38, 0x30 }, { CR34, 0x0f }, { CR35, 0xF0 },
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{ CR41, 0x2a }, { CR46, 0x7F }, { CR47, 0x1E },
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{ CR51, 0xc5 }, { CR52, 0xc5 }, { CR53, 0xc5 },
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{ CR79, 0x58 }, { CR80, 0x30 }, { CR81, 0x30 },
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{ CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
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{ CR85, 0x00 }, { CR86, 0x10 }, { CR87, 0x2A },
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{ CR88, 0x10 }, { CR89, 0x24 }, { CR90, 0x18 },
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/* { CR91, 0x18 }, */
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/* should solve continous CTS frame problems */
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{ CR91, 0x00 },
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{ CR92, 0x0a }, { CR93, 0x00 }, { CR94, 0x01 },
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{ CR95, 0x00 }, { CR96, 0x40 }, { CR97, 0x37 },
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{ CR98, 0x05 }, { CR99, 0x28 }, { CR100, 0x00 },
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{ CR101, 0x13 }, { CR102, 0x27 }, { CR103, 0x27 },
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{ CR104, 0x18 }, { CR105, 0x12 },
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/* normal size */
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{ CR106, 0x1a },
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/* { CR106, 0x22 }, */
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{ CR107, 0x24 }, { CR108, 0x0a }, { CR109, 0x13 },
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{ CR110, 0x2F }, { CR111, 0x27 }, { CR112, 0x27 },
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{ CR113, 0x27 }, { CR114, 0x27 }, { CR115, 0x40 },
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{ CR116, 0x40 }, { CR117, 0xF0 }, { CR118, 0xF0 },
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{ CR119, 0x16 },
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/* no TX continuation */
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{ CR122, 0x00 },
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/* { CR122, 0xff }, */
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{ CR127, 0x03 }, { CR131, 0x08 }, { CR138, 0x28 },
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{ CR148, 0x44 }, { CR150, 0x10 }, { CR169, 0xBB },
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{ CR170, 0xBB },
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};
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static const u32 rv[] = {
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0x000007, /* REG0(CFG1) */
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0x07dd43, /* REG1(IFPLL1) */
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0x080959, /* REG2(IFPLL2) */
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0x0e6666,
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0x116a57, /* REG4 */
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0x17dd43, /* REG5 */
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0x1819f9, /* REG6 */
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0x1e6666,
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0x214554,
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0x25e7fa,
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0x27fffa,
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/* The Zydas driver somehow forgets to set this value. It's
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* only set for Japan. We are using internal power control
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* for now.
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*/
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0x294128, /* internal power */
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/* 0x28252c, */ /* External control TX power */
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/* CR31_CCK, CR51_6-36M, CR52_48M, CR53_54M */
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0x2c0000,
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0x300000,
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0x340000, /* REG13(0xD) */
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0x381e0f, /* REG14(0xE) */
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/* Bogus, RF2959's data sheet doesn't know register 27, which is
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* actually referenced here. The commented 0x11 is 17.
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*/
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0x6c180f, /* REG27(0x11) */
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};
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r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
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if (r)
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return r;
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return zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
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}
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static int rf2959_set_channel(struct zd_rf *rf, u8 channel)
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{
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int i, r;
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const u32 *rv = rf2959_table[channel-1];
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struct zd_chip *chip = zd_rf_to_chip(rf);
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for (i = 0; i < 2; i++) {
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r = zd_rfwrite_locked(chip, rv[i], RF_RV_BITS);
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if (r)
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return r;
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}
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return 0;
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}
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static int rf2959_switch_radio_on(struct zd_rf *rf)
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{
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static const struct zd_ioreq16 ioreqs[] = {
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{ CR10, 0x89 },
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{ CR11, 0x00 },
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};
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struct zd_chip *chip = zd_rf_to_chip(rf);
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return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
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}
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static int rf2959_switch_radio_off(struct zd_rf *rf)
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{
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static const struct zd_ioreq16 ioreqs[] = {
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{ CR10, 0x15 },
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{ CR11, 0x81 },
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};
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struct zd_chip *chip = zd_rf_to_chip(rf);
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return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
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}
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int zd_rf_init_rf2959(struct zd_rf *rf)
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{
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struct zd_chip *chip = zd_rf_to_chip(rf);
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if (chip->is_zd1211b) {
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dev_err(zd_chip_dev(chip),
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"RF2959 is currently not supported for ZD1211B"
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" devices\n");
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return -ENODEV;
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}
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rf->init_hw = rf2959_init_hw;
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rf->set_channel = rf2959_set_channel;
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rf->switch_radio_on = rf2959_switch_radio_on;
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rf->switch_radio_off = rf2959_switch_radio_off;
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return 0;
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}
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