forked from luck/tmp_suning_uos_patched
9b791d4766
This patch fixes cache memory parameter setting for the M32104 target. So
far, its performance seemed to have been degraded due to incorrect cache
parameter setting.
* arch/m32r/boot/setup.S: Set SFR(Special Fuction Registers) region
to be non-cachable explicitly.
* arch/m32r/mm/cache.c: Fix cache flushing routines not to switch off
the M32104 cache.
Signed-off-by: Hayato Fujiwara <fujiwara@linux-m32r.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
/*
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* linux/arch/m32r/mm/cache.c
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*
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* Copyright (C) 2002-2005 Hirokazu Takata, Hayato Fujiwara
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*/
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#include <linux/config.h>
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#include <asm/pgtable.h>
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#undef MCCR
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#if defined(CONFIG_CHIP_XNUX2) || defined(CONFIG_CHIP_M32700) \
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|| defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_OPSP)
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/* Cache Control Register */
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#define MCCR ((volatile unsigned long*)0xfffffffc)
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#define MCCR_CC (1UL << 7) /* Cache mode modify bit */
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#define MCCR_IIV (1UL << 6) /* I-cache invalidate */
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#define MCCR_DIV (1UL << 5) /* D-cache invalidate */
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#define MCCR_DCB (1UL << 4) /* D-cache copy back */
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#define MCCR_ICM (1UL << 1) /* I-cache mode [0:off,1:on] */
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#define MCCR_DCM (1UL << 0) /* D-cache mode [0:off,1:on] */
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#define MCCR_ICACHE_INV (MCCR_CC|MCCR_IIV)
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#define MCCR_DCACHE_CB (MCCR_CC|MCCR_DCB)
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#define MCCR_DCACHE_CBINV (MCCR_CC|MCCR_DIV|MCCR_DCB)
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#define CHECK_MCCR(mccr) (mccr = *MCCR)
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#elif defined(CONFIG_CHIP_M32102)
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#define MCCR ((volatile unsigned char*)0xfffffffe)
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#define MCCR_IIV (1UL << 0) /* I-cache invalidate */
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#define MCCR_ICACHE_INV MCCR_IIV
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#elif defined(CONFIG_CHIP_M32104)
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#define MCCR ((volatile unsigned short*)0xfffffffe)
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#define MCCR_IIV (1UL << 8) /* I-cache invalidate */
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#define MCCR_DIV (1UL << 9) /* D-cache invalidate */
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#define MCCR_DCB (1UL << 10) /* D-cache copy back */
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#define MCCR_ICM (1UL << 0) /* I-cache mode [0:off,1:on] */
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#define MCCR_DCM (1UL << 1) /* D-cache mode [0:off,1:on] */
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#define MCCR_ICACHE_INV MCCR_IIV
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#define MCCR_DCACHE_CB MCCR_DCB
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#define MCCR_DCACHE_CBINV (MCCR_DIV|MCCR_DCB)
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#endif
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#ifndef MCCR
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#error Unknown cache type.
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#endif
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/* Copy back and invalidate D-cache and invalidate I-cache all */
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void _flush_cache_all(void)
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{
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#if defined(CONFIG_CHIP_M32102)
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unsigned char mccr;
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*MCCR = MCCR_ICACHE_INV;
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#elif defined(CONFIG_CHIP_M32104)
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unsigned short mccr;
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/* Copyback and invalidate D-cache */
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/* Invalidate I-cache */
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*MCCR |= (MCCR_ICACHE_INV | MCCR_DCACHE_CBINV);
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#else
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unsigned long mccr;
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/* Copyback and invalidate D-cache */
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/* Invalidate I-cache */
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*MCCR = MCCR_ICACHE_INV | MCCR_DCACHE_CBINV;
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#endif
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while ((mccr = *MCCR) & MCCR_IIV); /* loop while invalidating... */
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}
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/* Copy back D-cache and invalidate I-cache all */
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void _flush_cache_copyback_all(void)
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{
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#if defined(CONFIG_CHIP_M32102)
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unsigned char mccr;
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*MCCR = MCCR_ICACHE_INV;
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#elif defined(CONFIG_CHIP_M32104)
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unsigned short mccr;
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/* Copyback and invalidate D-cache */
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/* Invalidate I-cache */
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*MCCR |= (MCCR_ICACHE_INV | MCCR_DCACHE_CB);
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#else
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unsigned long mccr;
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/* Copyback D-cache */
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/* Invalidate I-cache */
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*MCCR = MCCR_ICACHE_INV | MCCR_DCACHE_CB;
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#endif
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while ((mccr = *MCCR) & MCCR_IIV); /* loop while invalidating... */
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}
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