forked from luck/tmp_suning_uos_patched
9a9952bbd7
This time the IOMMU updates are mostly cleanups or fixes. No big new
features or drivers this time. In particular the changes include:
* Bigger cleanup of the Domain<->IOMMU data structures and the
code that manages them in the Intel VT-d driver. This makes
the code easier to understand and maintain, and also easier to
keep the data structures in sync. It is also a preparation
step to make use of default domains from the IOMMU core in the
Intel VT-d driver.
* Fixes for a couple of DMA-API misuses in ARM IOMMU drivers,
namely in the ARM and Tegra SMMU drivers.
* Fix for a potential buffer overflow in the OMAP iommu driver's
debug code
* A couple of smaller fixes and cleanups in various drivers
* One small new feature: Report domain-id usage in the Intel
VT-d driver to easier detect bugs where these are leaked.
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Merge tag 'iommu-updates-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu updates for from Joerg Roedel:
"This time the IOMMU updates are mostly cleanups or fixes. No big new
features or drivers this time. In particular the changes include:
- Bigger cleanup of the Domain<->IOMMU data structures and the code
that manages them in the Intel VT-d driver. This makes the code
easier to understand and maintain, and also easier to keep the data
structures in sync. It is also a preparation step to make use of
default domains from the IOMMU core in the Intel VT-d driver.
- Fixes for a couple of DMA-API misuses in ARM IOMMU drivers, namely
in the ARM and Tegra SMMU drivers.
- Fix for a potential buffer overflow in the OMAP iommu driver's
debug code
- A couple of smaller fixes and cleanups in various drivers
- One small new feature: Report domain-id usage in the Intel VT-d
driver to easier detect bugs where these are leaked"
* tag 'iommu-updates-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (83 commits)
iommu/vt-d: Really use upper context table when necessary
x86/vt-d: Fix documentation of DRHD
iommu/fsl: Really fix init section(s) content
iommu/io-pgtable-arm: Unmap and free table when overwriting with block
iommu/io-pgtable-arm: Move init-fn declarations to io-pgtable.h
iommu/msm: Use BUG_ON instead of if () BUG()
iommu/vt-d: Access iomem correctly
iommu/vt-d: Make two functions static
iommu/vt-d: Use BUG_ON instead of if () BUG()
iommu/vt-d: Return false instead of 0 in irq_remapping_cap()
iommu/amd: Use BUG_ON instead of if () BUG()
iommu/amd: Make a symbol static
iommu/amd: Simplify allocation in irq_remapping_alloc()
iommu/tegra-smmu: Parameterize number of TLB lines
iommu/tegra-smmu: Factor out tegra_smmu_set_pde()
iommu/tegra-smmu: Extract tegra_smmu_pte_get_use()
iommu/tegra-smmu: Use __GFP_ZERO to allocate zeroed pages
iommu/tegra-smmu: Remove PageReserved manipulation
iommu/tegra-smmu: Convert to use DMA API
iommu/tegra-smmu: smmu_flush_ptc() wants device addresses
...
122 lines
2.3 KiB
C
122 lines
2.3 KiB
C
/*
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* Copyright (C) 2014 NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __SOC_TEGRA_MC_H__
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#define __SOC_TEGRA_MC_H__
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#include <linux/types.h>
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struct clk;
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struct device;
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struct page;
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struct tegra_smmu_enable {
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unsigned int reg;
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unsigned int bit;
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};
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struct tegra_mc_timing {
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unsigned long rate;
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u32 *emem_data;
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};
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/* latency allowance */
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struct tegra_mc_la {
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unsigned int reg;
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unsigned int shift;
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unsigned int mask;
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unsigned int def;
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};
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struct tegra_mc_client {
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unsigned int id;
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const char *name;
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unsigned int swgroup;
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unsigned int fifo_size;
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struct tegra_smmu_enable smmu;
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struct tegra_mc_la la;
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};
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struct tegra_smmu_swgroup {
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const char *name;
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unsigned int swgroup;
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unsigned int reg;
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};
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struct tegra_smmu_soc {
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const struct tegra_mc_client *clients;
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unsigned int num_clients;
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const struct tegra_smmu_swgroup *swgroups;
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unsigned int num_swgroups;
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bool supports_round_robin_arbitration;
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bool supports_request_limit;
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unsigned int num_tlb_lines;
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unsigned int num_asids;
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};
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struct tegra_mc;
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struct tegra_smmu;
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#ifdef CONFIG_TEGRA_IOMMU_SMMU
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struct tegra_smmu *tegra_smmu_probe(struct device *dev,
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const struct tegra_smmu_soc *soc,
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struct tegra_mc *mc);
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void tegra_smmu_remove(struct tegra_smmu *smmu);
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#else
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static inline struct tegra_smmu *
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tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc,
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struct tegra_mc *mc)
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{
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return NULL;
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}
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static inline void tegra_smmu_remove(struct tegra_smmu *smmu)
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{
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}
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#endif
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struct tegra_mc_soc {
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const struct tegra_mc_client *clients;
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unsigned int num_clients;
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const unsigned long *emem_regs;
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unsigned int num_emem_regs;
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unsigned int num_address_bits;
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unsigned int atom_size;
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u8 client_id_mask;
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const struct tegra_smmu_soc *smmu;
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};
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struct tegra_mc {
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struct device *dev;
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struct tegra_smmu *smmu;
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void __iomem *regs;
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struct clk *clk;
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int irq;
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const struct tegra_mc_soc *soc;
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unsigned long tick;
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struct tegra_mc_timing *timings;
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unsigned int num_timings;
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};
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void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
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unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
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#endif /* __SOC_TEGRA_MC_H__ */
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