forked from luck/tmp_suning_uos_patched
78 lines
2.0 KiB
C
78 lines
2.0 KiB
C
/*
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* linux/arch/arm/mm/copypage-v4wt.S
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*
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* Copyright (C) 1995-1999 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is for CPUs with a writethrough cache and 'flush ID cache' is
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* the only supported cache operation.
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*/
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#include <linux/init.h>
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#include <asm/page.h>
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/*
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* ARMv4 optimised copy_user_page
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*
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* Since we have writethrough caches, we don't have to worry about
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* dirty data in the cache. However, we do have to ensure that
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* subsequent reads are up to date.
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*/
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void __attribute__((naked))
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v4wt_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
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{
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asm("\
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stmfd sp!, {r4, lr} @ 2\n\
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mov r2, %0 @ 1\n\
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ldmia r1!, {r3, r4, ip, lr} @ 4\n\
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1: stmia r0!, {r3, r4, ip, lr} @ 4\n\
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ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\
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stmia r0!, {r3, r4, ip, lr} @ 4\n\
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ldmia r1!, {r3, r4, ip, lr} @ 4\n\
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stmia r0!, {r3, r4, ip, lr} @ 4\n\
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ldmia r1!, {r3, r4, ip, lr} @ 4\n\
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subs r2, r2, #1 @ 1\n\
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stmia r0!, {r3, r4, ip, lr} @ 4\n\
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ldmneia r1!, {r3, r4, ip, lr} @ 4\n\
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bne 1b @ 1\n\
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mcr p15, 0, r2, c7, c7, 0 @ flush ID cache\n\
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ldmfd sp!, {r4, pc} @ 3"
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:
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: "I" (PAGE_SIZE / 64));
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}
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/*
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* ARMv4 optimised clear_user_page
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*
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* Same story as above.
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*/
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void __attribute__((naked))
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v4wt_clear_user_page(void *kaddr, unsigned long vaddr)
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{
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asm("\
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str lr, [sp, #-4]!\n\
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mov r1, %0 @ 1\n\
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mov r2, #0 @ 1\n\
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mov r3, #0 @ 1\n\
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mov ip, #0 @ 1\n\
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mov lr, #0 @ 1\n\
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1: stmia r0!, {r2, r3, ip, lr} @ 4\n\
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stmia r0!, {r2, r3, ip, lr} @ 4\n\
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stmia r0!, {r2, r3, ip, lr} @ 4\n\
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stmia r0!, {r2, r3, ip, lr} @ 4\n\
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subs r1, r1, #1 @ 1\n\
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bne 1b @ 1\n\
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mcr p15, 0, r2, c7, c7, 0 @ flush ID cache\n\
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ldr pc, [sp], #4"
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:
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: "I" (PAGE_SIZE / 64));
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}
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struct cpu_user_fns v4wt_user_fns __initdata = {
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.cpu_clear_user_page = v4wt_clear_user_page,
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.cpu_copy_user_page = v4wt_copy_user_page,
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};
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