forked from luck/tmp_suning_uos_patched
d7cf0edb8f
The per-processor interrupt request register and current processor priority register are only accessed on the current cpu. In fact the hypervisor doesn't even let us choose which cpu's registers to access. The only function to use cpu twice is xics_migrate_irqs_away, not a fast path. But we can cache the result of get_hard_processor_id() instead of calling get_hard_smp_processor_id(cpu) in a loop across the call to rtas. Years ago the irq code passed smp_processor_id into get_irq, I thought we might initialize the CPPR third party at boot as an extra measure of saftey, and it made the code symmetric with the qirr (queued interrupt for software generated interrupts), but now it is just extra and sometimes unneeded work to pass it down. Signed-off-by: Milton Miller <miltonm@bga.com> Signed-off-by: Paul Mackerras <paulus@samba.org> |
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