forked from luck/tmp_suning_uos_patched
f5ee256792
xtensa has 2-level page tables and already uses pgtable-nopmd for page
table folding.
Add walks of p4d level where appropriate and drop usage of
__ARCH_USE_5LEVEL_HACK.
Signed-off-by: Mike Rapoport <rppt@linux.ibm.com>
Message-Id: <1572964400-16542-3-git-send-email-rppt@kernel.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> [fix up
arch/xtensa/include/asm/fixmap.h and
arch/xtensa/mm/tlb.c]
120 lines
3.0 KiB
C
120 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* xtensa mmu stuff
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*
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* Extracted from init.c
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*/
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#include <linux/memblock.h>
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#include <linux/percpu.h>
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#include <linux/init.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/cache.h>
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#include <asm/tlb.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu_context.h>
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#include <asm/page.h>
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#include <asm/initialize_mmu.h>
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#include <asm/io.h>
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#if defined(CONFIG_HIGHMEM)
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static void * __init init_pmd(unsigned long vaddr, unsigned long n_pages)
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{
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pgd_t *pgd = pgd_offset_k(vaddr);
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p4d_t *p4d = p4d_offset(pgd, vaddr);
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pud_t *pud = pud_offset(p4d, vaddr);
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pmd_t *pmd = pmd_offset(pud, vaddr);
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pte_t *pte;
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unsigned long i;
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n_pages = ALIGN(n_pages, PTRS_PER_PTE);
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pr_debug("%s: vaddr: 0x%08lx, n_pages: %ld\n",
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__func__, vaddr, n_pages);
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pte = memblock_alloc_low(n_pages * sizeof(pte_t), PAGE_SIZE);
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if (!pte)
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panic("%s: Failed to allocate %lu bytes align=%lx\n",
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__func__, n_pages * sizeof(pte_t), PAGE_SIZE);
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for (i = 0; i < n_pages; ++i)
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pte_clear(NULL, 0, pte + i);
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for (i = 0; i < n_pages; i += PTRS_PER_PTE, ++pmd) {
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pte_t *cur_pte = pte + i;
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BUG_ON(!pmd_none(*pmd));
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set_pmd(pmd, __pmd(((unsigned long)cur_pte) & PAGE_MASK));
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BUG_ON(cur_pte != pte_offset_kernel(pmd, 0));
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pr_debug("%s: pmd: 0x%p, pte: 0x%p\n",
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__func__, pmd, cur_pte);
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}
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return pte;
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}
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static void __init fixedrange_init(void)
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{
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init_pmd(__fix_to_virt(0), __end_of_fixed_addresses);
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}
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#endif
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void __init paging_init(void)
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{
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#ifdef CONFIG_HIGHMEM
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fixedrange_init();
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pkmap_page_table = init_pmd(PKMAP_BASE, LAST_PKMAP);
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kmap_init();
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#endif
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}
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/*
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* Flush the mmu and reset associated register to default values.
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*/
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void init_mmu(void)
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{
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#if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
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/*
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* Writing zeros to the instruction and data TLBCFG special
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* registers ensure that valid values exist in the register.
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*
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* For existing PGSZID<w> fields, zero selects the first element
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* of the page-size array. For nonexistent PGSZID<w> fields,
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* zero is the best value to write. Also, when changing PGSZID<w>
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* fields, the corresponding TLB must be flushed.
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*/
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set_itlbcfg_register(0);
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set_dtlbcfg_register(0);
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#endif
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init_kio();
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local_flush_tlb_all();
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/* Set rasid register to a known value. */
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set_rasid_register(ASID_INSERT(ASID_USER_FIRST));
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/* Set PTEVADDR special register to the start of the page
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* table, which is in kernel mappable space (ie. not
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* statically mapped). This register's value is undefined on
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* reset.
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*/
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set_ptevaddr_register(XCHAL_PAGE_TABLE_VADDR);
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}
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void init_kio(void)
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{
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#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && defined(CONFIG_OF)
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/*
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* Update the IO area mapping in case xtensa_kio_paddr has changed
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*/
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write_dtlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
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XCHAL_KIO_CACHED_VADDR + 6);
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write_itlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
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XCHAL_KIO_CACHED_VADDR + 6);
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write_dtlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
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XCHAL_KIO_BYPASS_VADDR + 6);
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write_itlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
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XCHAL_KIO_BYPASS_VADDR + 6);
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#endif
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}
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