forked from luck/tmp_suning_uos_patched
3c835670ab
Arrange the sections in the FRV arch so that a BRA instruction with a 16-bit displacement can always reach from the trap table to entry.S, tlb-miss.S and break.S. The problem otherwise is that the linker can insert sufficient code between the slots in the trap table and the targets of the branch instructions in those slots that the displacement field in the instruction isn't sufficiently large. This is because the branch targets were in the .text section along with most of the other code in the kernel. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> |
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| .. | ||
| cache-page.c | ||
| dma-alloc.c | ||
| elf-fdpic.c | ||
| extable.c | ||
| fault.c | ||
| highmem.c | ||
| init.c | ||
| kmap.c | ||
| Makefile | ||
| mmu-context.c | ||
| pgalloc.c | ||
| tlb-flush.S | ||
| tlb-miss.S | ||
| unaligned.c | ||