forked from luck/tmp_suning_uos_patched
96f1050d3d
Bill Gatliff & David Brownell pointed out we were missing some copyrights, and licensing terms in some of the files in ./arch/blackfin, so this fixes things, and cleans them up. It also removes: - verbose GPL text(refer to the top level ./COPYING file) - file names (you are looking at the file) - bug url (it's in the ./MAINTAINERS file) - "or later" on GPL-2, when we did not have that right It also allows some Blackfin-specific assembly files to be under a BSD like license (for people to use them outside of Linux). Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
54 lines
2.1 KiB
C
54 lines
2.1 KiB
C
/*
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* Copyright 2005-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*
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* Set up the interrupt priorities
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*/
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <asm/blackfin.h>
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void __init program_IAR(void)
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{
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/* Program the IAR0 Register with the configured priority */
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bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
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((CONFIG_IRQ_DMA_ERROR - 7) << IRQ_DMA_ERROR_POS) |
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((CONFIG_IRQ_ERROR - 7) << IRQ_ERROR_POS) |
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((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
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((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
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((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
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((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
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((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS));
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bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
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((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
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((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
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((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
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((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS) |
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((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
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((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
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((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
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bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
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((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
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((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
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((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
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((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
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((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
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((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
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((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
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bfin_write_SIC_IAR3(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
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((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
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((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
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((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) |
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((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
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((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
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((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
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((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
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SSYNC();
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}
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