forked from luck/tmp_suning_uos_patched
dd4969a892
Split mvsas driver into multiple source codes, based on the split and function distribution found in Marvell's mvsas update. Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
119 lines
2.9 KiB
C
119 lines
2.9 KiB
C
#ifndef _MV_CHIPS_H_
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#define _MV_CHIPS_H_
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#define mr32(reg) readl(regs + MVS_##reg)
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#define mw32(reg,val) writel((val), regs + MVS_##reg)
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#define mw32_f(reg,val) do { \
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writel((val), regs + MVS_##reg); \
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readl(regs + MVS_##reg); \
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} while (0)
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static inline u32 mvs_cr32(void __iomem *regs, u32 addr)
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{
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mw32(CMD_ADDR, addr);
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return mr32(CMD_DATA);
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}
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static inline void mvs_cw32(void __iomem *regs, u32 addr, u32 val)
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{
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mw32(CMD_ADDR, addr);
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mw32(CMD_DATA, val);
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}
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static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
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{
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void __iomem *regs = mvi->regs;
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return (port < 4)?mr32(P0_SER_CTLSTAT + port * 4):
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mr32(P4_SER_CTLSTAT + (port - 4) * 4);
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}
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static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
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{
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void __iomem *regs = mvi->regs;
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if (port < 4)
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mw32(P0_SER_CTLSTAT + port * 4, val);
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else
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mw32(P4_SER_CTLSTAT + (port - 4) * 4, val);
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}
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static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off, u32 off2, u32 port)
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{
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void __iomem *regs = mvi->regs + off;
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void __iomem *regs2 = mvi->regs + off2;
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return (port < 4)?readl(regs + port * 8):
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readl(regs2 + (port - 4) * 8);
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}
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static inline void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,
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u32 port, u32 val)
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{
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void __iomem *regs = mvi->regs + off;
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void __iomem *regs2 = mvi->regs + off2;
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if (port < 4)
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writel(val, regs + port * 8);
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else
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writel(val, regs2 + (port - 4) * 8);
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}
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static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
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{
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return mvs_read_port(mvi, MVS_P0_CFG_DATA,
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MVS_P4_CFG_DATA, port);
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}
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static inline void mvs_write_port_cfg_data(struct mvs_info *mvi, u32 port, u32 val)
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{
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mvs_write_port(mvi, MVS_P0_CFG_DATA,
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MVS_P4_CFG_DATA, port, val);
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}
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static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi, u32 port, u32 addr)
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{
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mvs_write_port(mvi, MVS_P0_CFG_ADDR,
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MVS_P4_CFG_ADDR, port, addr);
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}
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static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
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{
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return mvs_read_port(mvi, MVS_P0_VSR_DATA,
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MVS_P4_VSR_DATA, port);
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}
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static inline void mvs_write_port_vsr_data(struct mvs_info *mvi, u32 port, u32 val)
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{
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mvs_write_port(mvi, MVS_P0_VSR_DATA,
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MVS_P4_VSR_DATA, port, val);
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}
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static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi, u32 port, u32 addr)
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{
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mvs_write_port(mvi, MVS_P0_VSR_ADDR,
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MVS_P4_VSR_ADDR, port, addr);
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}
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static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
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{
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return mvs_read_port(mvi, MVS_P0_INT_STAT,
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MVS_P4_INT_STAT, port);
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}
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static inline void mvs_write_port_irq_stat(struct mvs_info *mvi, u32 port, u32 val)
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{
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mvs_write_port(mvi, MVS_P0_INT_STAT,
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MVS_P4_INT_STAT, port, val);
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}
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static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
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{
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return mvs_read_port(mvi, MVS_P0_INT_MASK,
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MVS_P4_INT_MASK, port);
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}
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static inline void mvs_write_port_irq_mask(struct mvs_info *mvi, u32 port, u32 val)
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{
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mvs_write_port(mvi, MVS_P0_INT_MASK,
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MVS_P4_INT_MASK, port, val);
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}
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#endif
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