forked from luck/tmp_suning_uos_patched
1141d9d081
The BayTrail and CherryTrail platforms provide platform clocks through their Power Management Controller (PMC). The SoC supports up to 6 clocks (PMC_PLT_CLK[0..5]) with a frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail and a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks are available for general system use, where appropriate, and each have Control & Frequency register fields associated with them. Port from legacy by Pierre Bossart, integration in clock framework by Irina Tirdea Signed-off-by: Irina Tirdea <irina.tirdea@intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
4 lines
121 B
Makefile
4 lines
121 B
Makefile
clk-x86-lpss-objs := clk-lpt.o
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obj-$(CONFIG_X86_INTEL_LPSS) += clk-x86-lpss.o
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obj-$(CONFIG_PMC_ATOM) += clk-pmc-atom.o
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