forked from luck/tmp_suning_uos_patched
e04b0ea2e0
Some PCI adapters (eg. ipr scsi adapters) have an exposure today in that they issue BIST to the adapter to reset the card. If, during the time it takes to complete BIST, userspace attempts to access PCI config space, the host bus bridge will master abort the access since the ipr adapter does not respond on the PCI bus for a brief period of time when running BIST. On PPC64 hardware, this master abort results in the host PCI bridge isolating that PCI device from the rest of the system, making the device unusable until Linux is rebooted. This patch is an attempt to close that exposure by introducing some blocking code in the PCI code. When blocked, writes will be humored and reads will return the cached value. Ben Herrenschmidt has also mentioned that he plans to use this in PPC power management. Signed-off-by: Brian King <brking@us.ibm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> drivers/pci/access.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci-sysfs.c | 20 +++++----- drivers/pci/pci.h | 7 +++ drivers/pci/proc.c | 28 +++++++-------- drivers/pci/syscall.c | 14 +++---- include/linux/pci.h | 7 +++ 6 files changed, 134 insertions(+), 31 deletions(-)
152 lines
4.4 KiB
C
152 lines
4.4 KiB
C
#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/ioport.h>
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/*
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* This interrupt-safe spinlock protects all accesses to PCI
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* configuration space.
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*/
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static DEFINE_SPINLOCK(pci_lock);
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/*
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* Wrappers for all PCI configuration access functions. They just check
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* alignment, do locking and call the low-level functions pointed to
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* by pci_dev->ops.
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*/
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#define PCI_byte_BAD 0
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#define PCI_word_BAD (pos & 1)
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#define PCI_dword_BAD (pos & 3)
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#define PCI_OP_READ(size,type,len) \
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int pci_bus_read_config_##size \
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(struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
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{ \
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int res; \
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unsigned long flags; \
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u32 data = 0; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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spin_lock_irqsave(&pci_lock, flags); \
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res = bus->ops->read(bus, devfn, pos, len, &data); \
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*value = (type)data; \
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spin_unlock_irqrestore(&pci_lock, flags); \
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return res; \
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}
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#define PCI_OP_WRITE(size,type,len) \
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int pci_bus_write_config_##size \
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(struct pci_bus *bus, unsigned int devfn, int pos, type value) \
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{ \
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int res; \
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unsigned long flags; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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spin_lock_irqsave(&pci_lock, flags); \
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res = bus->ops->write(bus, devfn, pos, len, value); \
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spin_unlock_irqrestore(&pci_lock, flags); \
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return res; \
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}
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PCI_OP_READ(byte, u8, 1)
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PCI_OP_READ(word, u16, 2)
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PCI_OP_READ(dword, u32, 4)
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PCI_OP_WRITE(byte, u8, 1)
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PCI_OP_WRITE(word, u16, 2)
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PCI_OP_WRITE(dword, u32, 4)
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EXPORT_SYMBOL(pci_bus_read_config_byte);
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EXPORT_SYMBOL(pci_bus_read_config_word);
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EXPORT_SYMBOL(pci_bus_read_config_dword);
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EXPORT_SYMBOL(pci_bus_write_config_byte);
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EXPORT_SYMBOL(pci_bus_write_config_word);
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EXPORT_SYMBOL(pci_bus_write_config_dword);
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static u32 pci_user_cached_config(struct pci_dev *dev, int pos)
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{
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u32 data;
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data = dev->saved_config_space[pos/sizeof(dev->saved_config_space[0])];
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data >>= (pos % sizeof(dev->saved_config_space[0])) * 8;
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return data;
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}
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#define PCI_USER_READ_CONFIG(size,type) \
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int pci_user_read_config_##size \
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(struct pci_dev *dev, int pos, type *val) \
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{ \
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unsigned long flags; \
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int ret = 0; \
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u32 data = -1; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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spin_lock_irqsave(&pci_lock, flags); \
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if (likely(!dev->block_ucfg_access)) \
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ret = dev->bus->ops->read(dev->bus, dev->devfn, \
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pos, sizeof(type), &data); \
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else if (pos < sizeof(dev->saved_config_space)) \
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data = pci_user_cached_config(dev, pos); \
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spin_unlock_irqrestore(&pci_lock, flags); \
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*val = (type)data; \
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return ret; \
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}
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#define PCI_USER_WRITE_CONFIG(size,type) \
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int pci_user_write_config_##size \
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(struct pci_dev *dev, int pos, type val) \
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{ \
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unsigned long flags; \
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int ret = -EIO; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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spin_lock_irqsave(&pci_lock, flags); \
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if (likely(!dev->block_ucfg_access)) \
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ret = dev->bus->ops->write(dev->bus, dev->devfn, \
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pos, sizeof(type), val); \
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spin_unlock_irqrestore(&pci_lock, flags); \
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return ret; \
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}
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PCI_USER_READ_CONFIG(byte, u8)
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PCI_USER_READ_CONFIG(word, u16)
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PCI_USER_READ_CONFIG(dword, u32)
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PCI_USER_WRITE_CONFIG(byte, u8)
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PCI_USER_WRITE_CONFIG(word, u16)
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PCI_USER_WRITE_CONFIG(dword, u32)
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/**
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* pci_block_user_cfg_access - Block userspace PCI config reads/writes
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* @dev: pci device struct
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*
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* This function blocks any userspace PCI config accesses from occurring.
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* When blocked, any writes will be bit bucketed and reads will return the
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* data saved using pci_save_state for the first 64 bytes of config
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* space and return 0xff for all other config reads.
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**/
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void pci_block_user_cfg_access(struct pci_dev *dev)
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{
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unsigned long flags;
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pci_save_state(dev);
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/* spinlock to synchronize with anyone reading config space now */
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spin_lock_irqsave(&pci_lock, flags);
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dev->block_ucfg_access = 1;
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spin_unlock_irqrestore(&pci_lock, flags);
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}
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EXPORT_SYMBOL_GPL(pci_block_user_cfg_access);
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/**
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* pci_unblock_user_cfg_access - Unblock userspace PCI config reads/writes
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* @dev: pci device struct
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*
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* This function allows userspace PCI config accesses to resume.
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**/
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void pci_unblock_user_cfg_access(struct pci_dev *dev)
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{
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unsigned long flags;
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/* spinlock to synchronize with anyone reading saved config space */
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spin_lock_irqsave(&pci_lock, flags);
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dev->block_ucfg_access = 0;
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spin_unlock_irqrestore(&pci_lock, flags);
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}
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EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access);
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