forked from luck/tmp_suning_uos_patched
751605152b
For the sake of consistency, let rename all ctrl_out/in calls to the write/read calls so we have the same API consistent with the other architectures hence open the door for the increasing of the test compilation coverage. The unsigned long coercive cast is removed because all variables are set to the right type "void __iomem *". Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
94 lines
1.9 KiB
C
94 lines
1.9 KiB
C
/*
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* H8/300H interrupt controller driver
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*
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* Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/io.h>
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static const char ipr_bit[] = {
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7, 6, 5, 5,
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4, 4, 4, 4, 3, 3, 3, 3,
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2, 2, 2, 2, 1, 1, 1, 1,
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0, 0, 0, 0, 15, 15, 15, 15,
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14, 14, 14, 14, 13, 13, 13, 13,
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-1, -1, -1, -1, 11, 11, 11, 11,
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10, 10, 10, 10, 9, 9, 9, 9,
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};
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static void __iomem *intc_baseaddr;
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#define IPR (intc_baseaddr + 6)
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static void h8300h_disable_irq(struct irq_data *data)
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{
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int bit;
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int irq = data->irq - 12;
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bit = ipr_bit[irq];
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if (bit >= 0) {
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if (bit < 8)
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ctrl_bclr(bit & 7, IPR);
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else
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ctrl_bclr(bit & 7, (IPR+1));
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}
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}
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static void h8300h_enable_irq(struct irq_data *data)
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{
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int bit;
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int irq = data->irq - 12;
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bit = ipr_bit[irq];
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if (bit >= 0) {
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if (bit < 8)
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ctrl_bset(bit & 7, IPR);
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else
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ctrl_bset(bit & 7, (IPR+1));
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}
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}
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struct irq_chip h8300h_irq_chip = {
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.name = "H8/300H-INTC",
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.irq_enable = h8300h_enable_irq,
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.irq_disable = h8300h_disable_irq,
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};
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static int irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw_irq_num)
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{
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irq_set_chip_and_handler(virq, &h8300h_irq_chip, handle_simple_irq);
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return 0;
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}
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static struct irq_domain_ops irq_ops = {
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.map = irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static int __init h8300h_intc_of_init(struct device_node *intc,
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struct device_node *parent)
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{
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struct irq_domain *domain;
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intc_baseaddr = of_iomap(intc, 0);
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BUG_ON(!intc_baseaddr);
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/* All interrupt priority low */
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writeb(0x00, IPR + 0);
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writeb(0x00, IPR + 1);
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domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL);
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BUG_ON(!domain);
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irq_set_default_host(domain);
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return 0;
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}
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IRQCHIP_DECLARE(h8300h_intc, "renesas,h8300h-intc", h8300h_intc_of_init);
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