forked from luck/tmp_suning_uos_patched
66314223aa
Adding core definitions for Altera's SOCFPGA ARM platform. Mininum support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
52 lines
2.0 KiB
C
52 lines
2.0 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#define SOCFPGA_OSC1_CLK 10000000
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#define SOCFPGA_MPU_CLK 800000000
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#define SOCFPGA_MAIN_QSPI_CLK 432000000
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#define SOCFPGA_MAIN_NAND_SDMMC_CLK 250000000
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#define SOCFPGA_S2F_USR_CLK 125000000
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void __init socfpga_init_clocks(void)
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{
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struct clk *clk;
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clk = clk_register_fixed_rate(NULL, "osc1_clk", NULL, CLK_IS_ROOT, SOCFPGA_OSC1_CLK);
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clk_register_clkdev(clk, "osc1_clk", NULL);
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clk = clk_register_fixed_rate(NULL, "mpu_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK);
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clk_register_clkdev(clk, "mpu_clk", NULL);
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clk = clk_register_fixed_rate(NULL, "main_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
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clk_register_clkdev(clk, "main_clk", NULL);
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clk = clk_register_fixed_rate(NULL, "dbg_base_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
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clk_register_clkdev(clk, "dbg_base_clk", NULL);
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clk = clk_register_fixed_rate(NULL, "main_qspi_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_QSPI_CLK);
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clk_register_clkdev(clk, "main_qspi_clk", NULL);
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clk = clk_register_fixed_rate(NULL, "main_nand_sdmmc_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_NAND_SDMMC_CLK);
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clk_register_clkdev(clk, "main_nand_sdmmc_clk", NULL);
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clk = clk_register_fixed_rate(NULL, "s2f_usr_clk", NULL, CLK_IS_ROOT, SOCFPGA_S2F_USR_CLK);
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clk_register_clkdev(clk, "s2f_usr_clk", NULL);
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}
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