AcoSail/kernel_optimize_test
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e1c96c8620
kernel_optimize_test/arch/mips/bcm63xx
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Florian Fainelli e1c96c8620 MIPS: BCM63xx: Remove BCM6345 hacks to read base boot address 
Though BCM6345 does not technically have the same MPI register layout
than the other SoCs, reading the chip-select registers is done the same
way, and particularly for chip-select 0, which is the boot flash.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3009/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07 22:03:04 +00:00
..
boards MIPS: BCM63xx: Remove BCM6345 hacks to read base boot address 2011-12-07 22:03:04 +00:00
clk.c MIPS: BCM63XX: Add support for bcm6368 CPU. 2011-12-07 22:03:04 +00:00
cpu.c MIPS: BCM63xx: Fix SDRAM size computation for BCM6345 2011-12-07 22:03:04 +00:00
cs.c
dev-dsp.c
dev-enet.c
dev-pcmcia.c
dev-uart.c MIPS: BCM63XX: Add support for bcm6368 CPU. 2011-12-07 22:03:04 +00:00
dev-wdt.c
early_printk.c
gpio.c
irq.c MIPS: BCM63XX: Add support for bcm6368 CPU. 2011-12-07 22:03:04 +00:00
Kconfig MIPS: BCM63XX: Add support for bcm6368 CPU. 2011-12-07 22:03:04 +00:00
Makefile MIPS: BCM63xx: Migrate to new platform makefile style. 2010-08-05 13:25:54 +01:00
Platform MIPS: BCM63xx: Migrate to new platform makefile style. 2010-08-05 13:25:54 +01:00
prom.c MIPS: BCM63XX: Add support for bcm6368 CPU. 2011-12-07 22:03:04 +00:00
setup.c MIPS: BCM63XX: Add external irq support for non 6348 CPUs. 2011-12-07 22:03:04 +00:00
timer.c