Vince Hsu af7c388a9c clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2 ... Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when the DIS power domain is during up-powergating process but the clamp to this domain is not removed yet. That causes a timeout and aborts the power sequence, although the PLLD/PLLD2 has already locked. To remove the false alarm, we don't use the lock for PLLD/PLLD2. Just wait 1ms and treat the clocks as locked. Signed-off-by: Vince Hsu <vinceh@nvidia.com> Tested-by: Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2016-08-24 10:54:17 -07:00
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clk-audio-sync.c
clk-dfll.c
clk-dfll.h
clk-divider.c
clk-emc.c
clk-id.h
clk-periph-fixed.c
clk-periph-gate.c
clk-periph.c
clk-pll-out.c
clk-pll.c
clk-super.c
clk-tegra-audio.c
clk-tegra-fixed.c
clk-tegra-periph.c
clk-tegra-pmc.c
clk-tegra-super-gen4.c
clk-tegra20.c
clk-tegra30.c
clk-tegra114.c
clk-tegra124-dfll-fcpu.c
clk-tegra124.c
clk-tegra210.c
clk.c
clk.h
cvb.c
cvb.h
Kconfig
Makefile