forked from luck/tmp_suning_uos_patched
c658eac628
The Xtensa architecture allows to define custom instructions and registers. Registers that are bound to a coprocessor are only accessible if the corresponding enable bit is set, which allows to implement a 'lazy' context switch mechanism. Other registers needs to be saved and restore at the time of the context switch or during interrupt handling. This patch adds support for these additional states: - save and restore registers that are used by the compiler upon interrupt entry and exit. - context switch additional registers unbound to any coprocessor - 'lazy' context switch of registers bound to a coprocessor - ptrace interface to provide access to additional registers - update configuration files in include/asm-xtensa/variant-fsf Signed-off-by: Chris Zankel <chris@zankel.net>
29 lines
618 B
C
29 lines
618 B
C
/*
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* include/asm-xtensa/sigcontext.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2007 Tensilica Inc.
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*/
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#ifndef _XTENSA_SIGCONTEXT_H
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#define _XTENSA_SIGCONTEXT_H
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struct sigcontext {
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unsigned long sc_pc;
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unsigned long sc_ps;
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unsigned long sc_lbeg;
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unsigned long sc_lend;
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unsigned long sc_lcount;
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unsigned long sc_sar;
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unsigned long sc_acclo;
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unsigned long sc_acchi;
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unsigned long sc_a[16];
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void *sc_xtregs;
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};
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#endif /* _XTENSA_SIGCONTEXT_H */
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