forked from luck/tmp_suning_uos_patched
7f78322cdd
On K3 AM654x/J721E platforms the Port MII mode selection register(s) have similar format and placed in the System Control Module (SCM) module sequentially as one register per port, but, depending SOC and CPSW instance, the base offset and number of ports can be different. Hence, add possibility to retrieve number of ports and base registers offset from DT and support for max possible number of ports supported by K3 SoCs like J721E. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20200828201943.29155-4-grygorii.strashko@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org> |
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.. | ||
Kconfig | ||
Makefile | ||
phy-am654-serdes.c | ||
phy-da8xx-usb.c | ||
phy-dm816x-usb.c | ||
phy-gmii-sel.c | ||
phy-j721e-wiz.c | ||
phy-omap-control.c | ||
phy-omap-usb2.c | ||
phy-ti-pipe3.c | ||
phy-tusb1210.c | ||
phy-twl4030-usb.c |