forked from luck/tmp_suning_uos_patched
441f199a37
The Tegra clock driver is initialized during the ARM machine descriptor's .init_irq() hook. It can't be initialized earlier, since dynamic memory usage is required. It can't be initialized later, since the .init_timer() hook needs the clocks initialized. However, at this time, udelay() doesn't work. The Tegra clock initialization table may enable some PLLs. Enabling a PLL may require usage of udelay(). Hence, this can't happen right when the clock driver is initialized. To solve this, separate the clock driver initialization from the clock table processing, so they can execute at separate times. Signed-off-by: Stephen Warren <swarren@nvidia.com>
129 lines
3.0 KiB
C
129 lines
3.0 KiB
C
/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __LINUX_CLK_TEGRA_H_
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#define __LINUX_CLK_TEGRA_H_
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#include <linux/clk.h>
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/*
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* Tegra CPU clock and reset control ops
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*
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* wait_for_reset:
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* keep waiting until the CPU in reset state
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* put_in_reset:
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* put the CPU in reset state
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* out_of_reset:
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* release the CPU from reset state
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* enable_clock:
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* CPU clock un-gate
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* disable_clock:
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* CPU clock gate
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* rail_off_ready:
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* CPU is ready for rail off
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* suspend:
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* save the clock settings when CPU go into low-power state
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* resume:
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* restore the clock settings when CPU exit low-power state
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*/
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struct tegra_cpu_car_ops {
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void (*wait_for_reset)(u32 cpu);
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void (*put_in_reset)(u32 cpu);
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void (*out_of_reset)(u32 cpu);
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void (*enable_clock)(u32 cpu);
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void (*disable_clock)(u32 cpu);
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#ifdef CONFIG_PM_SLEEP
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bool (*rail_off_ready)(void);
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void (*suspend)(void);
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void (*resume)(void);
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#endif
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};
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extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
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static inline void tegra_wait_cpu_in_reset(u32 cpu)
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{
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if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
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return;
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tegra_cpu_car_ops->wait_for_reset(cpu);
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}
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static inline void tegra_put_cpu_in_reset(u32 cpu)
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{
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if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
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return;
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tegra_cpu_car_ops->put_in_reset(cpu);
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}
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static inline void tegra_cpu_out_of_reset(u32 cpu)
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{
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if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
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return;
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tegra_cpu_car_ops->out_of_reset(cpu);
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}
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static inline void tegra_enable_cpu_clock(u32 cpu)
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{
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if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
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return;
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tegra_cpu_car_ops->enable_clock(cpu);
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}
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static inline void tegra_disable_cpu_clock(u32 cpu)
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{
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if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
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return;
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tegra_cpu_car_ops->disable_clock(cpu);
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}
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#ifdef CONFIG_PM_SLEEP
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static inline bool tegra_cpu_rail_off_ready(void)
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{
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if (WARN_ON(!tegra_cpu_car_ops->rail_off_ready))
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return false;
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return tegra_cpu_car_ops->rail_off_ready();
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}
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static inline void tegra_cpu_clock_suspend(void)
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{
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if (WARN_ON(!tegra_cpu_car_ops->suspend))
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return;
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tegra_cpu_car_ops->suspend();
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}
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static inline void tegra_cpu_clock_resume(void)
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{
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if (WARN_ON(!tegra_cpu_car_ops->resume))
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return;
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tegra_cpu_car_ops->resume();
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}
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#endif
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void tegra_periph_reset_deassert(struct clk *c);
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void tegra_periph_reset_assert(struct clk *c);
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void tegra_clocks_init(void);
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void tegra_clocks_apply_init_table(void);
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#endif /* __LINUX_CLK_TEGRA_H_ */
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