forked from luck/tmp_suning_uos_patched
a79a9ad94a
Signed-off-by: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
31 lines
1.5 KiB
C
31 lines
1.5 KiB
C
#ifndef __ASM_MACH_REGS_INTC_H
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#define __ASM_MACH_REGS_INTC_H
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#include <mach/hardware.h>
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/*
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* Interrupt Controller
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*/
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#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
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#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
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#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
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#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
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#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
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#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
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#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
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#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
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#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
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#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
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#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
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#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
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#define ICIP3 __REG(0x40D00130) /* Interrupt Controller IRQ Pending Register 3 */
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#define ICMR3 __REG(0x40D00134) /* Interrupt Controller Mask Register 3 */
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#define ICLR3 __REG(0x40D00138) /* Interrupt Controller Level Register 3 */
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#define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */
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#define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */
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#endif /* __ASM_MACH_REGS_INTC_H */
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