forked from luck/tmp_suning_uos_patched
c2de1c3829
The Arcom Zeus CF slot requires the same kind of support as the Viper. To avoid code duplication, introduce a platform device that abstracts the differences. This also allows for the removal of the ugly export of viper_cf_rst(). Signed-off-by: Marc Zyngier <maz@misterjones.org> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
95 lines
3.0 KiB
C
95 lines
3.0 KiB
C
/*
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* arch/arm/mach-pxa/include/mach/viper.h
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*
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* Author: Ian Campbell
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* Created: Feb 03, 2003
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* Copyright: Arcom Control Systems.
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*
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* Maintained by Marc Zyngier <maz@misterjones.org>
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* <marc.zyngier@altran.com>
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*
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* Created based on lubbock.h:
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef ARCH_VIPER_H
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#define ARCH_VIPER_H
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#define VIPER_BOOT_PHYS PXA_CS0_PHYS
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#define VIPER_FLASH_PHYS PXA_CS1_PHYS
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#define VIPER_ETH_PHYS PXA_CS2_PHYS
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#define VIPER_USB_PHYS PXA_CS3_PHYS
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#define VIPER_ETH_DATA_PHYS PXA_CS4_PHYS
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#define VIPER_CPLD_PHYS PXA_CS5_PHYS
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#define VIPER_CPLD_BASE (0xf0000000)
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#define VIPER_PC104IO_BASE (0xf1000000)
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#define VIPER_USB_BASE (0xf1800000)
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#define VIPER_ETH_GPIO (0)
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#define VIPER_CPLD_GPIO (1)
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#define VIPER_USB_GPIO (2)
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#define VIPER_UARTA_GPIO (4)
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#define VIPER_UARTB_GPIO (3)
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#define VIPER_CF_CD_GPIO (32)
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#define VIPER_CF_RDY_GPIO (8)
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#define VIPER_BCKLIGHT_EN_GPIO (9)
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#define VIPER_LCD_EN_GPIO (10)
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#define VIPER_PSU_DATA_GPIO (6)
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#define VIPER_PSU_CLK_GPIO (11)
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#define VIPER_UART_SHDN_GPIO (12)
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#define VIPER_BRIGHTNESS_GPIO (16)
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#define VIPER_PSU_nCS_LD_GPIO (19)
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#define VIPER_UPS_GPIO (20)
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#define VIPER_CF_POWER_GPIO (82)
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#define VIPER_TPM_I2C_SDA_GPIO (26)
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#define VIPER_TPM_I2C_SCL_GPIO (27)
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#define VIPER_RTC_I2C_SDA_GPIO (83)
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#define VIPER_RTC_I2C_SCL_GPIO (84)
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#define VIPER_CPLD_P2V(x) ((x) - VIPER_CPLD_PHYS + VIPER_CPLD_BASE)
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#define VIPER_CPLD_V2P(x) ((x) - VIPER_CPLD_BASE + VIPER_CPLD_PHYS)
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#ifndef __ASSEMBLY__
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# define __VIPER_CPLD_REG(x) (*((volatile u16 *)VIPER_CPLD_P2V(x)))
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#endif
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/* board level registers in the CPLD: (offsets from CPLD_BASE) ... */
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/* ... Physical addresses */
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#define _VIPER_LO_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100000)
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#define _VIPER_ICR_PHYS (VIPER_CPLD_PHYS + 0x100002)
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#define _VIPER_HI_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100004)
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#define _VIPER_VERSION_PHYS (VIPER_CPLD_PHYS + 0x100006)
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#define VIPER_UARTA_PHYS (VIPER_CPLD_PHYS + 0x300010)
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#define VIPER_UARTB_PHYS (VIPER_CPLD_PHYS + 0x300000)
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#define _VIPER_SRAM_BASE (VIPER_CPLD_PHYS + 0x800000)
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/* ... Virtual addresses */
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#define VIPER_LO_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_LO_IRQ_STATUS)
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#define VIPER_HI_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_HI_IRQ_STATUS)
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#define VIPER_VERSION __VIPER_CPLD_REG(_VIPER_VERSION_PHYS)
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#define VIPER_ICR __VIPER_CPLD_REG(_VIPER_ICR_PHYS)
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/* Decode VIPER_VERSION register */
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#define VIPER_CPLD_REVISION(x) (((x) >> 5) & 0x7)
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#define VIPER_BOARD_VERSION(x) (((x) >> 3) & 0x3)
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#define VIPER_BOARD_ISSUE(x) (((x) >> 0) & 0x7)
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/* Interrupt and Configuration Register (VIPER_ICR) */
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/* This is a write only register. Only CF_RST is used under Linux */
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#define VIPER_ICR_RETRIG (1 << 0)
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#define VIPER_ICR_AUTO_CLR (1 << 1)
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#define VIPER_ICR_R_DIS (1 << 2)
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#define VIPER_ICR_CF_RST (1 << 3)
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#endif
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